Senior Integration Design Engineer – Fullchip & IP

Lattice Semiconductor Corp.; Manila; Hybrid; PHP 1,100,000 - 1,900,000; Full time

Job summary

Lattice Semiconductor Corp. in Manila, Philippines, is seeking an Integration Design Engineer to join the Silicon Integration Team.

You will integrate multiple IPs to realize full-chip designs, producing models and verification assets for sign‑off and collaborating with Architecture, SW, IP Design and Physical Design groups to meet timing and power goals. The role requires 5+ years in custom/digital design, strong Verilog/SystemVerilog expertise, and familiarity with FPGA/CPLD flows.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering.
• Minimum 5 years in custom and digital design implementation.
• Expertise in Verilog and SystemVerilog.
• FPGA/CPLD design and integration experience is a plus.

Responsibilities

• Integrate IPs to build the full-chip and deliver models, views, and collaterals for sign-off.
• Collaborate with Architecture, SW, IP Design and Physical Design teams to generate the full-chip floorplan.
• Produce full-chip synthesized netlist and full-chip schematics for sign-off.
• Conduct elaboration/compilation, synthesis, timing closure, power and performance analysis, and SPICE simulations.
• Perform full-chip tapeout audits (EMIR, NetERC, PDN, SSO) and debug with cross-functional teams.

Skills

Verilog

SystemVerilog

FPGA/CPLD

Digital design

Perl

TCL

Python

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

Xcelium

Genus

Innovus

Tempus

Job description

Lattice Semiconductor Corp. in Manila, Philippines, is seeking an Integration Design Engineer to join the Silicon Integration Team.

You will integrate multiple IPs to realize full-chip designs, producing models and verification assets for sign‑off and collaborating with Architecture, SW, IP Design and Physical Design groups to meet timing and power goals. The role requires 5+ years in custom/digital design, strong Verilog/SystemVerilog expertise, and familiarity with FPGA/CPLD flows.