Senior SoC/FPGA Design Verification Engineer

Lattice Semiconductor Corp.; Manila; In loco; PHP 1.200.000 - 1.900.000; Tempo pieno

Descrizione del lavoro

Lattice Semiconductor Corp. in Manila, Philippines, is seeking a Senior Design Verification Engineer to join our Silicon team.

You will develop verification plans, create SystemVerilog/UVM testbenches, and drive coverage for complex SoC blocks. You will collaborate with design, IP, and SW teams on aggressive schedules, use Cadence IES/ XCELIUM, Synopsys VCS, and Mentor Questa, and contribute to best practices in verification.

Competenze

• 6–10 years of Digital Design Verification related experience.
• Bachelor or Masters Degree in Computer Science, Computer Engineering, Electronics and Electrical Engineering.
• Experience in ASIC/FPGA/SoC verification or development cycle.
• Experience in simulation tools like Cadence IES/XCELIUM, Synopsys VCS or Mentor's Questa.
• Hands-on experience with Python, Perl or Shell Scripting, TCL and Make.
• Strong communication, analytical and documentation skills and ability to interface with other groups/site.

Mansioni

• Develop verification plans and clear metrics; measure progress against the plan.
• Verify design blocks, sub-systems, and full chip using assertion-based, formal, and directed tests.
• Develop SystemVerilog and C-based testbenches in a UVM environment; create BVFs and verification tools.
• Define and design verification regression environment; perform functional and code coverage.

Conoscenze

HDL/HVL languages

Python scripting

Debugging complex digital design

Communication skills

Formazione

Bachelor or Masters in Computer Science/Engineering

Strumenti

Cadence IES/XCELIUM

Synopsys VCS

Mentor Questa

TCL

Make

Descrizione del lavoro

Lattice Semiconductor Corp. in Manila, Philippines, is seeking a Senior Design Verification Engineer to join our Silicon team.

You will develop verification plans, create SystemVerilog/UVM testbenches, and drive coverage for complex SoC blocks. You will collaborate with design, IP, and SW teams on aggressive schedules, use Cadence IES/ XCELIUM, Synopsys VCS, and Mentor Questa, and contribute to best practices in verification.