Senior FPGA Architect: Multi-Gbps Verilog/SystemVerilog

Luxoft; Mexico; On-site; PHP 7,299,000 - 10,949,000; Full time

Job summary

Luxoft is seeking a Principal/Staff-level FPGA Engineer to own FPGA architecture for our state-of-the-art Communications Test & Measurement products. The role involves end-to-end architectural design, IP tradeoffs, floorplanning, and timing closure for multi-gigabit designs.

You will lead DFX approaches, use Verilog/SystemVerilog/VHDL, and act as the final escalation point for FPGA issues, while mentoring other engineers and driving cross-team debugging from silicon to board bring-up.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.
• Expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL.
• Deep hands-on expertise with FPGA transceivers, hard IP, and PLLs including timing closure, equalization, and link debugging at multi-Gbps rates.
• Experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
• Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
• Knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
• Experience with AMD or Altera FPGA devices and toolchains, including timing closure and floorplanning.
• Proven experience with formal verification and/or UVM-based verification methodologies.
• Track record of taking FPGA designs from architecture to volume production across HW/FW boundary.
• Version control experience using Git or similar tools.
• Excellent written/oral communication, mentoring ability, and global stakeholder collaboration.
• Strong analytical and organizational skills in fast-paced environments.

Responsibilities

• Own FPGA architecture for state-of-the-art Communications Test & Measurement products, including IP selection and tradeoffs.
• Define end-to-end architecture, floorplanning, timing closure strategies for multi-gigabit designs, and DFX approaches.
• Serve as final technical escalation point for FPGA design and debug, mentor engineers, and lead silicon/board bring-up issue resolution.

Skills

Verilog/SystemVerilog

VHDL

FPGA timing closure

Multi-Gbps SerDes

Ethernet/IP

UVM verification

Git version control

Mentoring

Education

BS/MS in Electrical/Computer Engineering

Tools

FPGA toolchains (Xilinx/Intel)

Verilog

SystemVerilog

VHDL

Job description

Luxoft is seeking a Principal/Staff-level FPGA Engineer to own FPGA architecture for our state-of-the-art Communications Test & Measurement products. The role involves end-to-end architectural design, IP tradeoffs, floorplanning, and timing closure for multi-gigabit designs.

You will lead DFX approaches, use Verilog/SystemVerilog/VHDL, and act as the final escalation point for FPGA issues, while mentoring other engineers and driving cross-team debugging from silicon to board bring-up.