Senior Digital Implementation Engineer

Xinyx Design; Manila; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Xinyx Design is seeking a Senior Digital Implementation Engineer in Manila to lead end-to-end digital implementation of complex ASIC/FPGA designs. You will drive synthesis, place & route, and timing closure, collaborating with RTL, verification, and physical design teams to meet stringent performance and area goals.

You will mentor junior engineers and help advance digital design flows and methodologies, using industry-standard tools and scripting for automation.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5-8 years of experience in digital design implementation.
• Proven experience with multiple complete design cycles, from RTL to GDSII.
• Proficiency in RTL design languages (Verilog/System Verilog).
• In-depth knowledge of synthesis, place and route, and static timing analysis methodologies.
• Familiarity with design for test (DFT) methodologies and tools.
• Experience with EDA tools (Synopsys Design Compiler, Cadence Innovus, Mentor Graphics).
• Strong scripting skills (Perl, Tcl, Python) for automation and tool integration.

Responsibilities

• Lead synthesis, place and route, and optimization of complex digital designs.
• Drive timing closure through static timing analysis and corner handling.
• Collaborate with RTL, verification, and physical design teams for integration.
• Develop and improve digital implementation methodologies and flows.
• Utilize EDA tools effectively for implementation tasks and automation.
• Identify and resolve implementation issues including DRC/LVS and timing violations.
• Maintain documentation of design processes and deliverables.
• Provide mentorship to junior engineers in digital design practices.

Skills

Digital design

RTL/Verilog

Scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Cadence Innovus

Mentor Graphics

Job description

Job Summary:
The Senior Digital Implementation Engineer is responsible for the end-to-end digital implementation of complex ASIC designs, including synthesis, place and route, and timing closure. This role requires strong technical skills and experience in digital design methodologies, along with a proven ability to work in a collaborative environment. The ideal candidate will lead implementation projects, mentor junior engineers, and drive continuous improvements in digital design flows and methodologies.

Key Responsibilities:

• Digital Design Implementation: Lead the synthesis, place and route, and optimization of complex digital designs, ensuring high performance, area efficiency, and low power consumption.
• Timing Closure: Perform static timing analysis and drive timing closure efforts for digital designs, identifying and resolving timing issues across multiple corners.
• Collaboration: Work closely with RTL designers, verification engineers, and physical design teams to ensure smooth integration and compliance with design specifications.
• Methodology Development: Develop and improve digital implementation methodologies and flows, including best practices for synthesis, place and route, and DFT.
• Tool Utilization: Utilize EDA tools (e.g., Synopsys Design Compiler, Cadence Innovus, or Mentor Graphics) effectively for implementation tasks and drive automation efforts for increased efficiency.
• Debugging and Troubleshooting: Identify and resolve implementation issues, including signal integrity, DRC/LVS errors, and timing violations, through thorough debugging and analysis.
• Documentation: Maintain comprehensive documentation of design processes, methodologies, and project deliverables, ensuring traceability and knowledge sharing.
• Mentorship: Provide technical guidance and mentorship to junior engineers, fostering their growth in digital design implementation and best practices.

Key Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Master's/PhD is a plus.
• 5-8 years of experience in digital design implementation, with a strong background in ASIC or FPGA design flows.
• Proven experience with multiple complete design cycles, from RTL to GDSII.
• Proficiency in RTL design languages (Verilog/System Verilog) and strong understanding of digital design concepts.
• In-depth knowledge of synthesis, place and route, and static timing analysis methodologies.
• Familiarity with design for test (DFT) methodologies and tools.
• Experience with EDA tools (e.g., Synopsys Design Compiler, Cadence Innovus, Mentor Graphics).
• Strong scripting skills (e.g., Perl, Tcl, Python) for automation and tool integration.

Nice to Have Skills:

• Experience with low-power design techniques and methodologies.
• Familiarity with advanced verification techniques (e.g., UVM, formal verification).
• Understanding of mixed-signal design considerations.
• Experience in customer-facing roles, providing technical support and addressing customer requirements.