Senior FPGA Architect: Multi-Gbps SerDes & T&M Lead

Luxoft; Mexico; On-site; MXN 1,200,000 - 1,900,000; Full time

Job summary

Luxoft seeks a Principal/Staff-level FPGA Engineer to own FPGA architecture for state-of-the-art Communications Test & Measurement products. You will define end-to-end FPGA architecture, make/buy IP tradeoffs, floorplanning, and timing-closure strategies for multi-gigabit designs using Verilog/SystemVerilog/VHDL.

The role requires deep, hands-on FPGA transceiver expertise, VHDL/Verilog, and proven track record from architecture to volume production.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with 12–15 years of relevant experience, including 5+ years architecting multi-Gbps designs.
• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL.
• Deep hands-on expertise with FPGA transceivers, hard IP, and PLLs, including timing closure and link debug at multi-Gbps rates.
• Experience closing timing and debugging Ethernet link-layer issues (10 Mbps to 1.6 Tbps) and IP stacks in production.
• Proven expertise with optical interfaces (SFP/QSF) in shipped products.
• Extensive experience with VLANs, MPLS, VPLS, and VoIP/IPTV.
• Proven FPGA toolchain experience on AMD or Altera devices with timing closure and floorplanning.
• Formal verification and/or UVM-based verification experience; ability to lead proof strategies.
• Track record of taking designs from architecture to volume production with HW/FW tradeoffs.
• Version control experience (Git or similar); strong communication skills for stakeholders.

Responsibilities

• Own FPGA architecture and drive end-to-end design for high-speed products.
• Define make/buy IP tradeoffs, floorplanning, and timing closure strategies for multi-Gbps designs.
• Serve as final technical escalation point for FPGA design and debugging issues.
• Mentor engineers and lead root-cause debug of silicon and board bring-up challenges.

Skills

FPGA design

Verilog/SystemVerilog

VHDL

Timing closure

SerDes/transceivers

IP/PLL design

Floorplanning

UVM verification

Ethernet 10M–1.6T

Optical interfaces

VLANs/MPLS/VPLS

PCIe

AMDis/Altera toolchains

Git/version control

Formal verification

Education

BS or MS in Electrical/Computer Engineering

Tools

Questa or similar

Aldec Riviera

Job description

Luxoft seeks a Principal/Staff-level FPGA Engineer to own FPGA architecture for state-of-the-art Communications Test & Measurement products. You will define end-to-end FPGA architecture, make/buy IP tradeoffs, floorplanning, and timing-closure strategies for multi-gigabit designs using Verilog/SystemVerilog/VHDL.

The role requires deep, hands-on FPGA transceiver expertise, VHDL/Verilog, and proven track record from architecture to volume production.