Senior Design Verification Engineer

VerificationTechnology Philippines Inc.; Philippines; On-site; PHP 335,000 - 670,000; Full time

Job summary

VerificationTechnology Philippines Inc. invites engineers to work on large-scale RTL design projects using Verilog HDL and VHDL. You will inspect architectures, design logic, verify timing paths, and optimize the critical path for performance.

Responsibilities include extracting verification items from specifications, creating testbenches, and verifying on the bench to ensure design correctness before tape-out. A strong background in digital design and HDL languages is essential.

Qualifications

• Bachelor’s degree in a relevant engineering or computer science field.

Responsibilities

• Design RTL blocks in Verilog HDL and VHDL for large-scale RTL designs.
• Extract verification items from the specification.
• Create testbenches and verify on the bench.

Skills

RTL design

Verilog HDL

VHDL

Testbench creation

Timing optimization

Logic verification

Architecture investigation

Education

Bachelor's degree in relevant field

Job description

• Large scale RTL design over 100k gate in Verilog HDL and VHDL, including architecture investigation, logic design, logic verification, timing optimization for the critical path
• Extracting the verification items from the specification
• Creating the testbench and verifying on the bench

Educational background

• Bachelor’s degree in computer engineering, electronics, electronics and communications engineering, computer science or similar course