Senior FPGA Developer

Luxoft; Mexico; On-site; PHP 7,304,000 - 11,564,000; Full time

Job summary

Luxoft is seeking a Principal/Staff-level FPGA Engineer to own FPGA architecture for state-of-the-art Communications Test & Measurement products. You will define end-to-end architecture, make/buy IP decisions, floorplan and time closure for multi-gigabit designs, and drive DFX with Verilog/SystemVerilog/VHDL tools.

You will serve as the final technical escalation point for FPGA design, mentor engineers, and lead root-cause debugging of silicon and board bring-up issues across the team.

Qualifications

• BS or MS in Electrical and/or Computer Engineering with 12–15 years of relevant experience, including 5+ years architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.
• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL.
• Deep hands-on expertise with FPGA transceivers, hard IP, and PLLs—timing closure, equalization, and link debug at multi-Gbps rates.

Responsibilities

• Define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• Serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues.

Skills

Verilog/SystemVerilog

VHDL

FPGA design

Timing closure

IP protocol stacks

Optical interfaces

Ethernet

UVM verification

Git

Mentoring

DFX

Education

BS in Electrical and/or Computer Engineering

MS in Electrical and/or Computer Engineering

Tools

Altera FPGA toolchain

AMD FPGA toolchain

Synthesis/Place&Route tools

UVM verification tools

Job description

About the Company: Working for a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. A leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.

About the Role: We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products.

Responsibilities:

• The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere.

Qualifications:

• BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.

Required Skills:

• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required.
• Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).
• Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
• Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
• Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
• Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
• Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed testbenches.
• Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
• Version control experience using Git or similar tools.
• Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
• Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.

Preferred Skills: Languages: English: B2 Upper Intermediate