Design Verification Engineer II - SoC/FPGA

Lattice Semiconductor Corp.; Manila; On-site; PHP 600,000 - 1,000,000; Full time

Job summary

Lattice Semiconductor is seeking a Design Verification Engineer in Manila to join the Silicon team. You will develop verification plans, verify blocks and full chips, and create SystemVerilog/C testbenches in UVM. Collaborate with design, IP, and SW teams to ensure high-quality SoC verification on aggressive schedules.

The role requires strong debugging skills, HDL/HVL experience, and proficiency with major simulation tools. Join a global leader in programmable logic and grow with a dynamic team.

Qualifications

• 5-8 years of digital design verification experience.
• Bachelor's or Master's in CS/CE/Electronics or EEE.
• Strong debugging and analysis skills for complex digital design.
• Experience in HDL and HVL languages and methodologies.
• Experience in ASIC/FPGA/SoC verification or development cycle.
• Knowledge of Cadence IES/Xcelium, Synopsys VCS or Mentor Questa.
• Hands-on Python, Perl or Shell scripting, TCL and Make.
• Strong communication, analytical and documentation skills.

Responsibilities

• Develop verification plans with clear metrics and track progress.
• Verify blocks, subsystems and full chip using assertions, formal, directed and randomized tests.
• Develop SystemVerilog and C-based testbenches in UVM environment.
• Build testbench components like UVCs, BFMs and verification tools.
• Define and design verification regression environment.
• Collaborate with design, IP and SW teams to deliver high-quality SoC verification.
• Achieve functional coverage, RTL code coverage, assertion coverage and gate-level simulations.

Skills

Digital verification

SystemVerilog

UVM

Python

HDL/HVL

Education

Bachelor's or Master's in Computer Science/Engineering or Electronics

Tools

Cadence IES/XCELIUM

Synopsys VCS

Mentor Questa

Job description

Lattice Semiconductor is seeking a Design Verification Engineer in Manila to join the Silicon team. You will develop verification plans, verify blocks and full chips, and create SystemVerilog/C testbenches in UVM. Collaborate with design, IP, and SW teams to ensure high-quality SoC verification on aggressive schedules.

The role requires strong debugging skills, HDL/HVL experience, and proficiency with major simulation tools. Join a global leader in programmable logic and grow with a dynamic team.