Field-Programmable Gate Arrays Engineer

Luxoft; Mexico; On-site; MXN 1,200,000 - 1,900,000; Full time

Job summary

Luxoft seeks a Principal/Staff-level FPGA Engineer to own FPGA architecture for state-of-the-art Communications Test & Measurement products. You will define end-to-end FPGA architecture, make/buy IP tradeoffs, floorplanning, and timing-closure strategies for multi-gigabit designs using Verilog/SystemVerilog/VHDL.

The role requires deep, hands-on FPGA transceiver expertise, VHDL/Verilog, and proven track record from architecture to volume production.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with 12–15 years of relevant experience, including 5+ years architecting multi-Gbps designs.
• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL.
• Deep hands-on expertise with FPGA transceivers, hard IP, and PLLs, including timing closure and link debug at multi-Gbps rates.
• Experience closing timing and debugging Ethernet link-layer issues (10 Mbps to 1.6 Tbps) and IP stacks in production.
• Proven expertise with optical interfaces (SFP/QSF) in shipped products.
• Extensive experience with VLANs, MPLS, VPLS, and VoIP/IPTV.
• Proven FPGA toolchain experience on AMD or Altera devices with timing closure and floorplanning.
• Formal verification and/or UVM-based verification experience; ability to lead proof strategies.
• Track record of taking designs from architecture to volume production with HW/FW tradeoffs.
• Version control experience (Git or similar); strong communication skills for stakeholders.

Responsibilities

• Own FPGA architecture and drive end-to-end design for high-speed products.
• Define make/buy IP tradeoffs, floorplanning, and timing closure strategies for multi-Gbps designs.
• Serve as final technical escalation point for FPGA design and debugging issues.
• Mentor engineers and lead root-cause debug of silicon and board bring-up challenges.

Skills

FPGA design

Verilog/SystemVerilog

VHDL

Timing closure

SerDes/transceivers

IP/PLL design

Floorplanning

UVM verification

Ethernet 10M–1.6T

Optical interfaces

VLANs/MPLS/VPLS

PCIe

AMDis/Altera toolchains

Git/version control

Formal verification

Education

BS or MS in Electrical/Computer Engineering

Tools

Questa or similar

Aldec Riviera

Job description

• 
  Working for a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. a leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications
• .Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers

Responsibiliti

• es:
  We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement produ
• cts.The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools. This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewh

Mandatory S

• kill
• s:
  F

Mandatory Skills Des

• cription:
  BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPG
• A designs.Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL
• required.Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental
• exposure).Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in productio
• n designs.Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped
• products.Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (Vo
• IP, IPTV).Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning t
• echniques.Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed te
• stbenches.Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW
• boundary.Version control experience using Git or simi
• lar tools.Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across
• the world.Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product en

vironment.

Nice-to-Have Skills

• Description:
  Patents or published work in FPGA architecture, high-speed digital de
• sign, or DSP.Experience defining test strategies for multi-Gbps compliance testing (particularly relevant for T&M product
• development).General purpose microprocessor and DSP systems, PCIe, high-speed digital board design, PLL design, and analog signal conditionin
• g experience.Simulation experience using Siemens Questa, Aldec Riviera, or s
• imilar tools.Contribution to or deep familiarity with open verification methodologies (e.g., cocotb, UVM community co
• ntributions).Utilization of generative AI tools to assist in concept and implementation of