Lead Low-Power & Formal Verification Engineer (ASIC/SoC)

Renesas Electronics Corporation; Hinoba-an; On-site; PHP 1,800,000 - 2,800,000; Full time

Job summary

Renesas Electronics Corporation seeks an experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) for ASIC/SoC programs. Define and sign off power intent, ensuring correct low-power implementation across RTL through tapeout.

You will collaborate with Architecture, RTL, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness and tapeout readiness, while driving automation for verification flows.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10–15 years of ASIC/SoC verification or implementation experience.
• Strong UPF/CPF low-power methodologies.
• Hands-on experience with Formal Equivalence Verification (FEV/LEC) tools.

Responsibilities

• Define, sign off power intent (UPF/CPF) and low-power architecture across IP to chip level.
• Drive formal equivalence verification from RTL to tapeout, including ECOs.
• Collaborate with Architecture, RTL, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams.
• Develop automation scripts for low-power validation and equivalence checks.
• Generate signoff-quality reports for milestone and tapeout reviews.
• Drive issue tracking and closure.

Skills

Low-power verification

Formal verification

Scripting languages

Debugging and analytical

Education

Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering

Tools

FEV/LEC tools

Job description

Renesas Electronics Corporation seeks an experienced engineer to lead Low Power (Power Intent) and Formal Equivalence Verification (FEV/LEC) for ASIC/SoC programs. Define and sign off power intent, ensuring correct low-power implementation across RTL through tapeout.

You will collaborate with Architecture, RTL, Synthesis, DFT, STA, Physical Design, PDN, and Signoff teams to ensure functional correctness and tapeout readiness, while driving automation for verification flows.