Senior Synthesis & Timing Engineer, SoC/ASIC

Renesas Electronics Corporation; Hinoba-an; On-site; PHP 1,500,000 - 2,300,000; Full time

Job summary

Renesas Electronics Corporation is seeking an experienced Synthesis and Timing Constraints Engineer to lead timing constraint development for complex SoC designs. You will collaborate with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.

The role emphasizes RTL synthesis optimization, constraint management, and flow enhancements.

Qualifications

• Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
• 10–15 years of experience in ASIC/SoC implementation.
• Expert knowledge of Synopsys Design Compiler and Fusion Compiler.
• Strong understanding of Static Timing Analysis (STA), timing closure, and SDC methodology.
• Hands-on scripting experience in Tcl and/or Python.
• Experience with advanced-node implementation flows.
• Strong analytical, problem-solving, and debugging skills.
• Ability to work effectively with global cross-functional teams.

Responsibilities

• Define, develop, and maintain timing constraints (SDC) at IP, subsystem, and chip levels.
• Drive RTL synthesis and optimization using Synopsys Design Compiler and Fusion Compiler.
• Analyze and resolve timing, area, power, and implementation challenges to achieve design targets.
• Collaborate with cross-functional teams to ensure robust design convergence throughout the implementation cycle.
• Develop and enhance methodologies, flows, and automation to improve productivity and design quality.
• Support timing closure activities and drive best practices for synthesis and constraint management.
• Debug and resolve synthesis and timing-related issues during project execution.
• Contribute to flow improvements for advanced-node ASIC/SoC development.

Skills

Synopsys Design Compiler

Fusion Compiler

STA

SDC

Tcl

Python

ASIC/SoC Implementation

Timing Constraints

Scripting

Education

Bachelor's/Master's in Electronics/Electrical

Tools

Synopsys Fusion Compiler

Synopsys Design Compiler

Job description

Renesas Electronics Corporation is seeking an experienced Synthesis and Timing Constraints Engineer to lead timing constraint development for complex SoC designs. You will collaborate with Architecture, RTL Design, Physical Design, and STA teams to deliver high-quality implementations across advanced technology nodes.

The role emphasizes RTL synthesis optimization, constraint management, and flow enhancements.