Senior SOC Verification Architect (AI‑Driven)

Renesas Electronics Corporation; Hinoba-an; On-site; PHP 1,000,000 - 1,500,000; Full time

Job summary

Renesas Electronics Corporation in the Philippines is seeking a senior SoC verification engineer to drive end-to-end verification of complex digital IPs and subsystems from spec to sign-off. You will design IP-level verification strategies and develop scalable UVM-based environments.

Collaborate with RTL, Architecture, Emulation, and SoC verification teams to ensure robust integration, apply AI/ML-assisted techniques to speed coverage, and mentor junior engineers while delivering high-quality

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering.
• 5–15 years in SoC verification using UVM-based testbenches.
• Strong SystemVerilog, Verilog, SVA knowledge and coverage metrics.
• Directed and constrained-random verification; debug across sims.
• Proficient in Python, C/C++, and shell scripting; strong communication.

Responsibilities

• Be part of end-to-end verification for SOC IPs from spec to sign-off.
• Define and drive IP-level verification strategies, plans, and closure criteria.
• Develop scalable UVM-based environments for IP and subsystem verification.
• Lead functional and code coverage closure with clear metrics.
• Apply AI/ML-assisted verification to speed convergence and reduce regressions.
• Collaborate with RTL, Architecture, Emulation, and SoC teams.
• Review IP specs to translate requirements into robust verification plans and checkers.
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors.

Skills

UVM verification

SystemVerilog

Code coverage

Verification planning

C/C++

Python

SVA/Assertions

Emulation

AI/ML verification

Education

Bachelor’s or Master’s in Electronics Engineering

Tools

EDA toolkits

Simulators

Job description

Renesas Electronics Corporation in the Philippines is seeking a senior SoC verification engineer to drive end-to-end verification of complex digital IPs and subsystems from spec to sign-off. You will design IP-level verification strategies and develop scalable UVM-based environments.

Collaborate with RTL, Architecture, Emulation, and SoC verification teams to ensure robust integration, apply AI/ML-assisted techniques to speed coverage, and mentor junior engineers while delivering high-quality