Remote Design Verification Engineer - Mixed-Signal

CAI; Filipinas; A distancia; PHP 600.000 - 1.200.000; Jornada completa

Descripción de la vacante

CAI is a global services firm providing engineering verification expertise and digital design services. We are seeking a Design Verification Engineer to develop test benches for mixed-signal product verification, ensuring regression coverage and reliability.

This full-time remote role offers opportunities to work with cross-functional teams and apply SystemVerilog/UVM methodologies. The candidate will create and maintain verification environments, collaborate on project timelines, and contribute

Formación

• Bachelor’s or Master’s degree in Electrical/EC/Computer Engineering or related field.
• 2–4 years of digital design verification experience.
• Proficient in SystemVerilog and UVM for complex verification.
• Experience developing test benches for mixed-signal verification.
• Scripting in Python, Perl, or TCL for automation.
• Strong RTL understanding and Verilog concepts.
• Experience with EDA tools and simulators.
• Ability to debug verification issues with limited supervision.

Responsabilidades

• Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies.
• Create verification plans and measure functional and code coverage metrics to ensure design quality.
• Debug verification issues using advanced troubleshooting techniques and provide effective solutions.
• Collaborate with design teams to align verification strategies with project requirements.

Conocimientos

SystemVerilog

UVM

Test benches

Python scripting

Verilog RTL

Digital verification

EDA tools

Debugging

Educación

Electrical/EC Eng degree

Herramientas

EDA tools

Descripción del empleo

CAI is a global services firm providing engineering verification expertise and digital design services. We are seeking a Design Verification Engineer to develop test benches for mixed-signal product verification, ensuring regression coverage and reliability.

This full-time remote role offers opportunities to work with cross-functional teams and apply SystemVerilog/UVM methodologies. The candidate will create and maintain verification environments, collaborate on project timelines, and contribute