Team Lead Digital Verification (SoC) - Visas Supported

European Tech Recruit; Randstad; On-site; EUR 90,000 - 150,000; Full time

Job summary

European Tech Recruit is seeking a Digital Verification Leader in the Netherlands to drive ASIC verification for SoCs. You will lead verification of digital IP blocks, develop test benches, and collaborate with backend teams to address timing, synthesis, and DFT issues.

You will guide the verification strategy and monitor regressions across multiple clock domains. The role requires 8+ years in ASIC verification, leadership experience, and strong skills in SystemVerilog, UVM, Verilog, and

Qualifications

• Bachelor's degree or higher in Electrical Engineering.
• 8+ years of experience as an ASIC Verification Engineer.
• A couple of years of experience as a team lead.
• Proficiency with Verilog and standard EDA tools.
• Experience with standard EDA tools like Cadence and Mentor.
• Experience designing complex mixed-signal products with analog blocks and microcontrollers.
• Experience with RTL and ultra-low-power designs; strong digital design flow knowledge.
• Understanding of synthesis, STA, and netlist verifications.
• Experience in digital backend flow for Floor Planning and Place & Route (PNR).
• Strong programming and scripting skills: MATLAB, C/C++, Tcl.

Responsibilities

• Verify ASIC digital IP blocks and simulate chip-level post-layout in upcoming SoCs.
• Develop test benches and test cases for block-level functional verification.
• Coordinate with backend and implementation teams to address synthesis, timing, DFT issues for ASIC implementation.
• Understand design integration activities like Lint, CDC, Synthesis & ECO.
• Define verification and test plans; run regressions and debug issues.
• Verify IPs/Sub IPs integrated into the top-level SoC.

Skills

SystemVerilog

UVM

Verilog

MATLAB

C/C++

Tcl

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Job description

A fantastic opportunity for a skilled Digital Verification Leader to join a pioneering Semiconductor Scale-up, who specialise in innovative Digital-RF based wireless scalable CMOS solutions and related IPs.

In this role, you'll play pivotal part in shaping the future of cutting-edge technology. You will be responsible for the verification of digital IP blocks and the simulation of Chip level post-layout within upcoming SoCs.

Aside from contributing to ground-breaking technology, you’re helping shape a team that’s redefining what it means to work in deep tech.

Job Description

• You are responsible for ASIC verification, System Verilog, and UVM.
• You will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management.
• You will develop test benches and test cases for block-level functional verification.
• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation.
• You understand all design integration activities like Lint, CDC, Synthesis & ECO.
• Define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.

Requirements

• Bachelor's degree or higher in Electrical Engineering
• 8+ years of experience as an ASIC Verification Engineer.
• A couple of years of experience as a team lead.
• Proficiency with EDA tools and design languages including Verilog.
• Experience with standard EDA tools like Candance and Mentor.
• You have experience in designing complex mixed-signal products containing analog building blocks and microcontrollers.
• You have worked with RTL and ultra-low-power designs before. Good knowledge of digital design flow from architecture design to sign-off
• You understand synthesis, static timing analysis, and netlist verifications
• You have some previous experience in digital backend flow for Floor Planning and Place & Route (PNR)
• You have strong programming and scripting skills: MATLAB, C/C++, Tcl
• Experience in setting up Power Distribution architecture, power intent specification and validation methodology.
• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation
• Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
• Strong analytical, problem-solving skills.

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