Senior ASIC Verification Lead - Digital IP & SoC

European Tech Recruit; Randstad; On-site; EUR 90,000 - 150,000; Full time

Job summary

European Tech Recruit is seeking a Digital Verification Leader in the Netherlands to drive ASIC verification for SoCs. You will lead verification of digital IP blocks, develop test benches, and collaborate with backend teams to address timing, synthesis, and DFT issues.

You will guide the verification strategy and monitor regressions across multiple clock domains. The role requires 8+ years in ASIC verification, leadership experience, and strong skills in SystemVerilog, UVM, Verilog, and

Qualifications

• Bachelor's degree or higher in Electrical Engineering.
• 8+ years of experience as an ASIC Verification Engineer.
• A couple of years of experience as a team lead.
• Proficiency with Verilog and standard EDA tools.
• Experience with standard EDA tools like Cadence and Mentor.
• Experience designing complex mixed-signal products with analog blocks and microcontrollers.
• Experience with RTL and ultra-low-power designs; strong digital design flow knowledge.
• Understanding of synthesis, STA, and netlist verifications.
• Experience in digital backend flow for Floor Planning and Place & Route (PNR).
• Strong programming and scripting skills: MATLAB, C/C++, Tcl.

Responsibilities

• Verify ASIC digital IP blocks and simulate chip-level post-layout in upcoming SoCs.
• Develop test benches and test cases for block-level functional verification.
• Coordinate with backend and implementation teams to address synthesis, timing, DFT issues for ASIC implementation.
• Understand design integration activities like Lint, CDC, Synthesis & ECO.
• Define verification and test plans; run regressions and debug issues.
• Verify IPs/Sub IPs integrated into the top-level SoC.

Skills

SystemVerilog

UVM

Verilog

MATLAB

C/C++

Tcl

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence

Mentor Graphics

Job description

European Tech Recruit is seeking a Digital Verification Leader in the Netherlands to drive ASIC verification for SoCs. You will lead verification of digital IP blocks, develop test benches, and collaborate with backend teams to address timing, synthesis, and DFT issues.

You will guide the verification strategy and monitor regressions across multiple clock domains. The role requires 8+ years in ASIC verification, leadership experience, and strong skills in SystemVerilog, UVM, Verilog, and