SoC Architect (Hybrid) - Visas Supported

European Tech Recruit; Randstad; On-site; EUR 110,000 - 140,000; Full time

Job summary

European Tech Recruit is seeking an experienced SOC Architect to join a pioneering semiconductor scale-up specialising in Digital-RF based wireless CMOS solutions and IPs. You will define the high-level SoC architecture and guide hardware/firmware integration to deliver scalable products.

In this role you will collaborate with design teams, ensure security features, manage timelines and budgets, and stay ahead of industry advances to keep the architecture future-proof for next generation devices.

Qualifications

• 10+ years experience in RTL design and verification.
• Deep understanding of ARM MCUs subsystems and memory architectures.
• 8 years’ experience with Digital ASIC flows, RTL design and DFT/JTAG techniques.
• Solid understanding of chip packaging and hardware-software interfaces.
• Experience with RFIC system design and analog-digital interfaces.

Responsibilities

• System Design & Integration and defining the high-level SoC architecture.
• Guide chip physical design with hardware teams and ensure firmware compatibility.
• Coordinate with GNSS team to support software execution and drivers.
• Define and implement security features for the SoC.
• Manage timelines and budgets, ensuring the project stays on track.
• Keep architecture scalable for future product generations.

Skills

RTL design

RTL verification

CPU architecture

ARM subsystems

Digital ASIC flows

Interface design

Debug & trace

Power efficiency

IP selection

Signal integrity

Job description

A fantastic opportunity for a skilled SOC Architect to join a pioneering Semiconductor Scale-up, who specialise in innovative Digital-RF based wireless scalable CMOS solutions and related IPs.

You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip. Aside from contributing to a ground-breaking technology, you will be helping shape a team that’s redefining what it means to work in deep tech.

Key Responsibilities

• System Design & Integration
• You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
• You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
• You will define and implement security features to protect the SoC from vulnerabilities.
• You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
• Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Requirements

• 10+ years experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).
• 8 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
• Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
• Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.
• Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
• Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
• Hands-on experience with IP selection to meet the specific needs of the design.
• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
• In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
• Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
• Solid Knowledge in signal processing, communication system.
• Exposure to all aspects of RFIC system design.

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