Mixed Signal Verification Engineer (UVM/SV) - CMOS - Visas Supported”

European Tech Recruit; Den Haag; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking an experienced Verification Engineer to join a market-leading MEMS timing company in Delft, The Netherlands. You will develop SV-RNM models, write SVA, and drive verification plans across analog/mixed-signal circuits, collaborating with dispersed teams.

The role requires a Bachelors in EE/CS with 6 years in semiconductor verification, strong SystemVerilog/UVM skills, Cadence Virtuoso familiarity, and scripting in Perl/Python to debug and optimize tape-out

Qualifications

• Bachelor's degree in electrical/computer engineering or related fields with 6 years of work experience in semiconductor verification.
• Proficient in SystemVerilog and SystemVerilog OOP.
• Strong experience writing SystemVerilog Assertions (SVA).
• Proficient in UVM verification methodology.
• Fluent in scripting languages (Perl / Python) for debugging.
• Familiar with digital design basics in Verilog and analog/mixed-signal context.

Responsibilities

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders to facilitate teamwork and exchange of ideas

Skills

SystemVerilog

SVA

UVM

Verilog

Cadence Virtuoso

Perl

Python

Education

Bachelor's degree in electrical/computer engineering or related fields

Tools

Cadence Virtuoso

Job description

A fantastic opportunity for an experienced Verification Engineer to join a market leading Semiconductor company, who specialise in MEMS precision timing.

This role will be performed alongside the team in Delft (The Netherlands), and the company can offer Visa and Relocation Support where required.

Responsibilities:

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas.
• Bachelors degree in electrical/computer engineering or related fields with 6 years of work experience doing verification in the semiconductor industry
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in utilizing scripting languages such as Perl / Python
• Proficient (through work experience) in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers

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