Senior Verification Engineer (AI / Chip Security) - Amsterdam

European Tech Recruit; Amsterdam; On-site; EUR 70,000 - 90,000; Full time

Job summary

A semiconductor manufacturer in Amsterdam is looking for an ASIC Verification Engineer to develop and maintain verification environments using UVM. The ideal candidate will have a Bachelor's or Master's degree and at least 5 years of ASIC verification experience. You will create verification plans, debug issues, and mentor junior team members while collaborating with other teams to align project goals. The role offers an exciting opportunity to improve methodologies in a fast-scaling environment.

Qualifications

• Minimum of 5 years of experience in ASIC verification.
• Experience with scripting languages like Python, Perl, or Tcl is a plus.

Responsibilities

• Develop and maintain UVM-based verification environments.
• Create verification plans and test cases.
• Implement and execute test benches.
• Debug issues and resolve them with design engineers.
• Drive improvement of verification methodologies.
• Mentor junior team members.
• Collaborate with other teams for alignment.
• Participate in design reviews.

Skills

Proficiency in SystemVerilog

Strong understanding of digital design concepts

Excellent problem-solving skills

Attention to detail

Ability to work independently and as part of a team

Excellent communication skills

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

UVM

Verilog

Digital design concepts

Job description

A fantastic opportunity for an experienced ASIC Verification Engineer to join a fast-scaling Semiconductor manufacturer based in Amsterdam, Netherlands.

Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. Collaborating closely with cross-functional teams including design, architecture, and software engineering to deliver high-quality solutions that meet or exceed customer expectations.

Responsibilities

• Develop and maintain UVM-based verification environments for complex digital designs.
• Create comprehensive verification plans and test cases based on design specifications.
• Implement and execute test benches to verify functionality, performance, and compliance with specifications.
• Debug issues and work closely with design engineers to resolve them in a timely manner.
• Drive continuous improvement of verification methodologies, processes, and best practices.
• Mentor junior team members and provide technical guidance as needed.
• Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals.
• Participate in design reviews and contribute to architectural decisions from a verification perspective.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 5 years of experience in ASIC verification.
• Proficiency in SystemVerilog, Verilog and UVM methodology.
• Strong understanding of digital design concepts and verification techniques.
• Excellent problem-solving skills and attention to detail.
• Ability to work effectively both independently and as part of a team.
• Excellent communication and interpersonal skills.
• Experience with scripting languages such as Python, Perl, or Tcl is a plus.

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