Team Lead Digital Verification

Visa Hunt; Netherlands; On-site; EUR 90,000 - 120,000; Full time

Job summary

Qualinx is seeking a Team Lead Digital ASIC Verification Engineer to shape the verification strategy for our next-generation SoCs. You will verify digital IP blocks, lead testbench creation, and collaborate with backend teams on timing and ECO issues.

The role emphasizes leading verification efforts, building robust environments, and ensuring high-quality digital designs through SystemVerilog and UVM expertise.

Qualifications

• Experience in ASIC verification of digital IPs and full-chip verification flow.
• Strong knowledge of SystemVerilog and UVM for testbench development.
• Ability to design, implement and maintain robust verification environments.

Responsibilities

• Verify digital IP blocks and RTL in simulation and post-layout contexts.
• Develop and maintain test benches and test cases for block-level verification.
• Coordinate with backend/implementation teams on timing, SDF, and ECO issues.
• Define and execute verification plans, regressions, and debugging across SoCs.

Skills

ASIC verification

SystemVerilog

UVM

RTL verification

Test benches

Debugging

Job description

Join our cutting-edge start-up adventure!

Who are we?

Join the Revolution in GNSS and IoT Connectivity

AtQualinx, we’re not just building chips, we’re engineering the future fabric of the connected world. As a pioneering semiconductor scale‑up, we’re transforming how devices connect, communicate, and operate through our ground‑breaking Digital RF technology. Our mission goes beyond ultra‑low power GNSS: we’re redefining what’s possible in adaptive, scalable, and intelligent connectivity for the Internet of Things.

Born from deep‑tech innovation at TU Delft, our team of visionary engineers and bold thinkers is tackling the toughest challenges in GNSS and IoT, starting with power consumption and expanding into dynamic, context‑aware solutions that adapt to any environment or use case. We’ve already achieved what many thought impossible: the world’s most advanced GNSS chipset. But that’s just the beginning.

At Qualinx, we believe that the future of connectivity lies in precision, efficiency, and adaptability. Our ambition is to become the invisible thread that seamlessly interconnects billions of devices: powering a smarter, more responsive world.

What Sets Us Apart

Joining Qualinx is about becoming part of a culture that’s as ambitious as it is authentic. We hold ourselves to high standards, thrive on solving the unexpected, and push boundaries together. But we also know how to enjoy the ride. Our culture is a unique blend of curiosity, team spirit, and a touch of unconventional charm. It’s fast‑paced, fun, and grounded in a sober sense of purpose and perspective. Whether we’re deep in design reviews or sharing laughs over lunch, we’re building something meaningful together. At Qualinx, you’re not just contributing to a ground‑breaking technology, you’re helping shape a team that’s redefining what it means to work in deep tech.

Job Description

As a Team Lead Digital ASIC Verification Engineer, you'll play a role in shaping the future of our cutting‑edge technology. You will be responsible for the verification of our digital IP blocks and the simulation of Chip level post‑layout within our upcoming SoCs. You will contribute to the circuit design for our next‑generation products.

• You are responsible for ASIC verification, System Verilog, and UVM.
• You will be responsible for the simulation and verification of digital block implementation in RTL for various functions, including control state machine digital processing (DSP), and multiple clock domain interface management.
• During your work at Qualinx you will be responsible for the post‑layout simulation of complex mixed‑signal SoC.
• As a Digital ASIC Verification engineer you will develop test benches and test cases for block–level functional verification.
• You will work with our backend and implementation teams to address synthesis, timing, DFT issues for the ASIC implementation.
• You understand all design integration activities like Lint, CDC, Synthesis & ECO.
• You will define the verification and test plan, run regressions, reproduce, and debug functional and performance bugs.
• You are responsible for the verification of various IPs/Sub IPs integrated to the top level SoC.
• Lastly: you will have an understanding of the design synthesis and fix timing issues for the Physical Design team.