Analog Mixed-Signal Design Engineer II - Precision Timing

SiTime; Rijswijk; On-site; EUR 90,000 - 140,000; Full time

Job summary

SiTime is seeking an Analog Mixed-Signal Circuit Design Engineer to advance precision timing circuits based on MEMS technology. The role spans networking, communications infrastructure, and mobile platforms, including wearables, with a focus on silicon-proven performance.

You'll design analog/mixed-signal blocks, collaborate with layout and product teams, implement verification and DFT/DFM, and help bring-up and characterize chips. A strong academic record and Cadence proficiency are required.

Qualifications

• MS or PhD in Electrical Engineering required.
• Proven knowledge of CMOS circuits and noise analysis.
• Proficient in Cadence analog design tools.
• Programming experience with MATLAB and VerilogA.

Responsibilities

• Design analog and mixed-signal circuits meeting architectural requirements and specifications.
• Contribute to architectural definition of the design and chip integration.
• Perform simulations and verification to ensure blocks meet specs at schematic level and after post-layout extraction (DFT/DFM).
• Collaborate with Layout Engineers to validate layout using best-known methods.
• Document blocks and run design reviews (preliminary and final).
• Participate in chip bring-up, evaluation and characterization of owned blocks.
• Cross-functionally work with Product, Characterization, Test and Applications Engineers on issues related to owned blocks.

Skills

MATLAB

VerilogA

Education

MS or Ph.D. in Electrical Engineering

Tools

Cadence analog design tools

Job description

SiTime is seeking an Analog Mixed-Signal Circuit Design Engineer to advance precision timing circuits based on MEMS technology. The role spans networking, communications infrastructure, and mobile platforms, including wearables, with a focus on silicon-proven performance.

You'll design analog/mixed-signal blocks, collaborate with layout and product teams, implement verification and DFT/DFM, and help bring-up and characterize chips. A strong academic record and Cadence proficiency are required.