Snr ASIC Design Engineer

Qblox; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

Qblox is seeking an experienced ASIC Design Engineer in Delft, Netherlands. In this role, you'll revolutionize quantum computing by taking ownership of cutting-edge designs, ensuring high-performance digital logic implementation, and collaborating with multidisciplinary teams to meet ambitious silicon delivery targets.

The ideal candidate has over 8 years of relevant experience, deep knowledge of RTL coding and digital design, and strong skills in EDA tools and scripting. Join us in shaping the future of quantum technology!

Qualifications

• 8+ years as a digital design engineer in R&D or fabless ASIC.
• Deep knowledge of digital design and IP development.
• Proficiency in scripting to automate workflows.
• Strong understanding of timing closure methodologies.

Responsibilities

• Evaluate system requirements for digital logic architecture.
• Drive designs through front-end ASIC flow.
• Write self-checking testbenches for verification.

Skills

Digital design engineering

RTL coding

VHDL

Verilog

Python

EDA tools

Static timing analysis

Communication skills

Tools

Git

MATLAB

Simulink

Job description

ASIC Design Engineer

Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world‑class research teams to build a cutting‑edge control stack for industrial‑scale quantum computers.

Our distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high‑frequency analog signals. Imagine what it takes to talk to 10,000 qubits with nanosecond‑level synchronization and all‑to‑all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon.

We foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed‑signal engineers, digital verification specialists, embedded software developers, and physicists.

Your Role

• Deconstruct requirements & design: evaluate system requirements to architect and implement robust, high‑performance digital logic and IP blocks.
• Front‑end flow ownership: drive designs through the front‑end ASIC flow, including RTL coding, linting, clock domain crossing (CDC) analysis, and initial synthesis.
• Verification collaboration: write block‑level self‑checking testbenches and collaborate with the verification team to expand top‑level UVM environments.
• Architectural influence: propose innovative changes to chip architecture, power‑saving strategies, and team methodologies.
• Cross‑functional sparring: act as a core technical sparring partner to a diverse engineering team, continuously pushing for better ways of doing things.

Enough about us, what about you?

To thrive in this role, you should bring:

• 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape‑outs/deliveries.
• Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.
• Strong experience with standard ASIC front‑end EDA tools, processor/bus‑system architectures (e.g., AMBA AXI/AHB protocols), and synthesis.
• Solid understanding of static timing analysis (STA) constraints and timing closure methodologies.
• Understanding of analog/mixed‑signal chips or IP (e.g., ADC/DAC interfaces, PLLs).
• Proficiency in scripting to automate design workflows (Python, Tcl, Shell) and version control (Git).
• Strong communication and collaboration skills.

Optional Nice‑to‑Haves

• Active experience with advanced verification frameworks (UVM).
• Prior experience with DFT (Design for Test) insertion, scan chains, and BIST.
• Experience with modelling and simulation in MATLAB / Simulink.
• Strong background in DSP and signal‑processing filters.
• Familiarity with AI agentic workflows and automation within the design flow.
• Experience or a strong interest in the Quantum Computing field.