Snr ASIC Design Engineer

Entangled Future; Delft; Hybrid; EUR 90,000 - 120,000; Full time

Job summary

Qblox in Delft, Netherlands is seeking a senior ASIC Design Engineer to architect and implement high‑performance digital logic and IP. You will drive RTL coding in Verilog/VHDL, lead tape-outs, and collaborate with mixed‑signal, verification, and embedded software teams.

Bring 8+ years in digital design, R&D or fabless ASIC, deep RTL knowledge, and a track record of silicon deliveries. You will influence architecture, power‑saving strategies, and engineering processes in a fast‑growing quantum

Qualifications

• 8+ years as a digital design engineer in an R&D or fabless ASIC environment.
• Deep fundamental knowledge of digital design, IP development, and RTL coding with VHDL/Verilog.

Responsibilities

• Architect and implement robust, high-performance digital logic and IP blocks.
• Drive RTL coding, linting, clock-domain crossing (CDC) analysis, and initial synthesis; collaborate on top-level UVM environments with verification.
• Propose innovative changes to chip architecture, power-saving strategies, and team methodologies.
• Act as a core technical sparring partner to a diverse engineering team across analog, digital verification, embedded software, and physics.

Skills

RTL coding

VHDL/Verilog

Digital design

Tape-out

Job description

Snr ASIC Design Engineer at Qblox, Delft, Zuid-Holland, Netherlands. A mid-level full time position in the FPGA Design team, listed under software engineering.

Join us at Qblox as we revolutionize the landscape of quantum computing! Our technology is used around the globe by world-class research teams to build a cutting-edge control stack for industrial-scale quantum computers. Our distributed architecture allows parallel qubit readout, control, and intercommunication, ultimately interacting with physical qubits using high-frequency analog signals. Imagine what it takes to talk to 10,000 qubits with nanosecond-level synchronization and all-to-all connectivity, and you will understand the massive microarchitectural, design, and verification challenges we face as we transition our logic to dedicated silicon. We foster a highly collaborative culture. You will take ownership of your projects, influence technical decisions, and work alongside analog/mixed-signal engineers, digital verification specialists, embedded software developers, and physicists.

architect and implement robust, high-performance digital logic and IP

blocks.

flow, including RTL coding, linting, clock domain crossing (CDC)

analysis, and initial synthesis. Verification Collaboration: Write block-level self-checking testbenches

and collaborate with the verification team to expand top-level UVM

environments.

Architectural Influence: Propose innovative changes to chip

architecture, power-saving strategies, and team methodologies. Cross-Functional Sparring: Act as a core technical sparring partner to a diverse engineering team, continuously pushing for better ways of doing things.

Enough about us, what about you?

To thrive in this role, you should bring

Experience: 8+ years as a digital design engineer within an R&D or fabless ASIC environment, with a proven track record of successful silicon tape-outs/deliveries. RTL & Architecture: Deep fundamental knowledge of digital design, IP development, and RTL coding using VHDL and/or Verilog.