Digital Verification Engineer

Entangled Future; Netherlands; Hybrid; EUR 65.000 - 90.000; Vollzeit

Zusammenfassung

Qblox, located in Delft, Netherlands, seeks a Digital Verification Engineer to strengthen RTL verification for FPGA/RTL modules and full systems.

You will collaborate with Digital Design and Embedded Software, building metric-driven testbenches and applying SystemVerilog/UVM and Python. Cocotb is encouraged as a tool in a culture of ownership and high-quality verification.

Qualifikationen

• 4+ years of experience in RTL verification within an R&D environment.
• Expertise in verification planning and implementing self-checking testbenches.
• Fluent in SystemVerilog/UVM and strong grasp of Python (OOP).

Aufgaben

• Own the Verification: Autonomously develop robust, metric-driven testbenches for complex FPGA/RTL modules and full systems.
• Bridge the Disciplines: Collaborate closely with Digital Design and Embedded Software engineers to analyze requirements and verify technical solutions.
• Interpret Complexity: Work with internal design specs and vendor documentation for FPGAs, third-party ASICs, and software.
• Drive Methodology: Proactively suggest and implement new tools, methodologies (like Cocotb), and advancements in the verification domain.
• Analyze & Evaluate: Understand and interpret VHDL code to ensure effective verification coverage while maintaining a collaborative loop with designers.

Kenntnisse

RTL verification

SystemVerilog/UVM

Python

Cocotb

Tools

Cocotb

Jobbeschreibung

Digital Verification Engineer at Qblox, Delft, Zuid-Holland, Netherlands. A mid-level full time position in the FPGA Verification team, listed under hardware engineering.

At Qblox, we are orchestrating the "brain" of the quantum computer. Our distributed control stacks allow for parallel qubit readout and nanosecond-level synchronization across massive architectures. Imagine the complexity of all-to-all connectivity for 1000 qubits, interacting with physical hardware via high-frequency analogue signals—that is the scale of the challenge our verification team faces. As we expand our R&D capabilities, we are looking for a Digital Verification Engineer to ensure our hardware is as reliable as the physics it controls.

The Role

You will be a key driver in our RTL verification strategy, developing robust, metric-driven testbenches at both the module and system levels. This is not a siloed role; you will act as a technical sparring partner for our Digital Design and Embedded Software teams, influencing architecture and processes by proposing improvements based on industry best practices. At Qblox, we foster a culture of ownership. You will have the opportunity to influence technical decisions at a high level and gain a deep understanding of the entire quantum control stack, learning from our in-house physics experts along the way.

Why Qblox? We offer a dynamic environment where engineering meets cutting-edge physics research. You\'ll be part of a highly international team that values inclusive knowledge exchange, technical ownership, and a healthy work-life balance.

Enough about us, what about you? To thrive in this environment, you likely possess a "first-principles" approach to problem-solving and a drive to see complex R&D projects through to completion.

• The Background: 4+ years of experience in RTL verification within an R&D environment.
• The Technical Core: Expertise in verification planning and implementing self-checking testbenches. You are fluent in SystemVerilog/UVM and have a strong grasp of Python (OOP).

Responsibilities

• Own the Verification: Autonomously develop robust, metric-driven testbenches for complex FPGA/RTL modules and full systems.
• Bridge the Disciplines: Collaborate closely with Digital Design and Embedded Software engineers to analyze requirements and verify technical solutions.
• Interpret Complexity: Work with internal design specs and vendor documentation for FPGAs, third-party ASICs, and software.
• Drive Methodology: Proactively suggest and implement new tools, methodologies (like Cocotb), and advancements in the verification domain.
• Analyze & Evaluate: Understand and interpret VHDL code to ensure effective verification coverage while maintaining a collaborative loop with designers.