Senior FPGA Design Engineer - Quantum Control Stack

Qblox; Delft; On-site; EUR 70,000 - 95,000; Full time

Job summary

Qblox in Delft develops cutting-edge quantum computing hardware and software stacks. We seek an experienced FPGA/RTL Design Engineer to design, verify, and optimize VHDL-based control systems for multi-qubit platforms, collaborating across electrical and software teams.

You will evaluate requirements, read vendor docs, and create robust testbenches while exploring architecture improvements and new FPGA/ASIC approaches to push performance and synchronization at nanosecond scales.

Qualifications

• 5+ years FPGA design in an R&D environment.
• Proficient reading of internal and vendor documentation.
• Strong VHDL knowledge and module-level verification experience.
• Experience with Xilinx Vivado or Intel Quartus.
• Knowledge of AMBA AXI and Avalon buses.
• Experience writing self-checking testbenches and UVM.
• Scripting skills in Python, Tcl/Tk, or shell.
• Git version control and collaboration in cross-functional teams.

Responsibilities

• Understand requirements, design solutions, and implement them in VHDL.
• Review internal and vendor documentation for FPGA/ASICs.
• Write self-checking module-level testbenches and contribute to top-level UVM testbenches.
• Propose architectural and process improvements within the team.
• Collaborate with a diverse, cross-functional FPGA and embedded software team.
• Proactively suggest new developments in the FPGA/ASIC field.

Skills

FPGA design

RTL design

VHDL

SystemVerilog

AMBA AXI

Avalon bus

Testbenches

UVM

Python scripting

Git

Communication

Tools

Xilinx Vivado

Intel Quartus

QuestaSim

Job description

Qblox in Delft develops cutting-edge quantum computing hardware and software stacks. We seek an experienced FPGA/RTL Design Engineer to design, verify, and optimize VHDL-based control systems for multi-qubit platforms, collaborating across electrical and software teams.

You will evaluate requirements, read vendor docs, and create robust testbenches while exploring architecture improvements and new FPGA/ASIC approaches to push performance and synchronization at nanosecond scales.