Senior Verification Engineer (AI / Chip Security) - Amsterdam

European Tech Recruit; Amsterdam; On-site; EUR 70,000 - 110,000; Full time

Job summary

European Tech Recruit is seeking an experienced ASIC Verification Engineer to join a fast-scaling semiconductor manufacturer in Amsterdam, Netherlands.

You will leverage UVM and systemVerilog verification to develop robust environments, collaborating with design, architecture, and software teams to meet customer requirements and drive high-quality results.

Qualifications

• Minimum 5 years of experience in ASIC verification.
• BSc or MSc in Electrical/Computer Engineering or related field.
• Strong proficiency in SystemVerilog, Verilog and UVM.

Responsibilities

• Develop and maintain UVM-based verification environments for complex digital designs.
• Create comprehensive verification plans and test cases based on design specs.
• Implement and execute test benches to verify functionality and performance.
• Debug issues and collaborate with design engineers for timely resolution.
• Drive continuous improvement of verification methodologies and best practices.
• Mentor junior team members and provide technical guidance.
• Collaborate with other teams to align verification with project timelines.

Skills

ASIC verification

Team collaboration

Problem solving

Education

Bachelor's or Master's degree in Electrical/Computer Engineering

Tools

SystemVerilog

Verilog

UVM

Python

Perl

Tcl

Job description

A fantastic opportunity for an experienced ASIC Verification Engineer to join a fast-scaling Semiconductor manufacturer based in Amsterdam, Netherlands.

Leveraging your extensive experience with Universal Verification Methodology (UVM) and verification techniques, you will contribute to the development of robust verification environments and methodologies. Collaborating closely with cross-functional teams including design, architecture, and software engineering to deliver high-quality solutions that meet or exceed customer expectations.

Responsibilities

• Develop and maintain UVM-based verification environments for complex digital designs.
• Create comprehensive verification plans and test cases based on design specifications.
• Implement and execute test benches to verify functionality, performance, and compliance with specifications.
• Debug issues and work closely with design engineers to resolve them in a timely manner.
• Drive continuous improvement of verification methodologies, processes, and best practices.
• Mentor junior team members and provide technical guidance as needed.
• Collaborate with other teams to ensure alignment of verification efforts with project timelines and goals.
• Participate in design reviews and contribute to architectural decisions from a verification perspective.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Minimum of 5 years of experience in ASIC verification.
• Proficiency in SystemVerilog, Verilog and UVM methodology.
• Strong understanding of digital design concepts and verification techniques.
• Excellent problem-solving skills and attention to detail.
• Ability to work effectively both independently and as part of a team.
• Excellent communication and interpersonal skills.
• Experience with scripting languages such as Python, Perl, or Tcl is a plus.

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