Senior ASIC Verification Engineer - AI/Chip Security

European Tech Recruit; Amsterdam; On-site; EUR 70,000 - 90,000; Full time

Job summary

A semiconductor manufacturer in Amsterdam is looking for an ASIC Verification Engineer to develop and maintain verification environments using UVM. The ideal candidate will have a Bachelor's or Master's degree and at least 5 years of ASIC verification experience. You will create verification plans, debug issues, and mentor junior team members while collaborating with other teams to align project goals. The role offers an exciting opportunity to improve methodologies in a fast-scaling environment.

Qualifications

• Minimum of 5 years of experience in ASIC verification.
• Experience with scripting languages like Python, Perl, or Tcl is a plus.

Responsibilities

• Develop and maintain UVM-based verification environments.
• Create verification plans and test cases.
• Implement and execute test benches.
• Debug issues and resolve them with design engineers.
• Drive improvement of verification methodologies.
• Mentor junior team members.
• Collaborate with other teams for alignment.
• Participate in design reviews.

Skills

Proficiency in SystemVerilog

Strong understanding of digital design concepts

Excellent problem-solving skills

Attention to detail

Ability to work independently and as part of a team

Excellent communication skills

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

UVM

Verilog

Digital design concepts

Job description

A semiconductor manufacturer in Amsterdam is looking for an ASIC Verification Engineer to develop and maintain verification environments using UVM. The ideal candidate will have a Bachelor's or Master's degree and at least 5 years of ASIC verification experience. You will create verification plans, debug issues, and mentor junior team members while collaborating with other teams to align project goals. The role offers an exciting opportunity to improve methodologies in a fast-scaling environment.