Verification Engineer (Mixed Signal/CMOS) - Visas Supported”

European Tech Recruit; Den Haag; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit is seeking an experienced Verification Engineer to join a market-leading semiconductor company in Delft, The Netherlands. You will develop SV-RNM models, create verification plans, and drive tape-out readiness.

The role requires 6 years of verification in semiconductors, strong SystemVerilog/SVA skills, and Cadence Virtuoso experience. You will collaborate with dispersed teams across design and test disciplines; visa/relocation support available.

Qualifications

• Bachelor's degree in electrical/computer engineering or related field.
• Minimum 6 years of verification experience in the semiconductor industry.
• Proficient in SystemVerilog and SystemVerilog OOP.
• Experience with UVM-based verification environments.
• Fluency with Perl and Python scripting.
• Knowledge of SystemVerilog Assertions (SVA) is essential.
• Familiarity with analog/mixed-signal verification and Cadence Virtuoso.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Create verification plans from chip or block specifications.
• Define and write SystemVerilog Assertions (SVA).
• Define and write functional coverages and covergroups.
• Run simulations and debug results.
• Review verification results for tape-out sign-off.
• Collaborate with design/test/verification stakeholders across dispersed teams.

Skills

SystemVerilog

UVM

SVA

Perl / Python

Cadence Virtuoso

Verilog

Tape-out

Scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Virtuoso

SystemVerilog Simulators

Job description

A fantastic opportunity for an experienced Verification Engineer to join a market leading Semiconductor company, who specialise in MEMS precision timing.

This role will be performed alongside the team in Delft (The Netherlands), and the company can offer Visa and Relocation Support where required.

Responsibilities:

• Developing SV-RNM models for both analog and mixed-signal circuits
• Developing verification plan from chip or block specifications
• Defining and writing System Verilog Assertions (SVA)
• Defining and writing functional coverages and covergroups
• Running simulations and debugging simulation results
• Reviewing verification results for Tape-out sign-off
• Communicating with stakeholders (design/test/verification) to facilitate teamwork and efficient sharing of information and exchange of ideas.
• Bachelors degree in electrical/computer engineering or related fields with 6 years of work experience doing verification in the semiconductor industry
• Proficient in SystemVerilog and SystemVerilog OOP
• Fluency in utilizing scripting languages such as Perl / Python
• Proficient (through work experience) in verification using UVM
• Strong experience writing SystemVerilog Assertions (SVA)
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Basic understanding of digital design using Verilog
• Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital design and analog design engineers

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