Lead Digital ASIC Verification Engineer

Visa Hunt; Netherlands; On-site; EUR 90,000 - 120,000; Full time

Job summary

Qualinx is seeking a Team Lead Digital ASIC Verification Engineer to shape the verification strategy for our next-generation SoCs. You will verify digital IP blocks, lead testbench creation, and collaborate with backend teams on timing and ECO issues.

The role emphasizes leading verification efforts, building robust environments, and ensuring high-quality digital designs through SystemVerilog and UVM expertise.

Qualifications

• Experience in ASIC verification of digital IPs and full-chip verification flow.
• Strong knowledge of SystemVerilog and UVM for testbench development.
• Ability to design, implement and maintain robust verification environments.

Responsibilities

• Verify digital IP blocks and RTL in simulation and post-layout contexts.
• Develop and maintain test benches and test cases for block-level verification.
• Coordinate with backend/implementation teams on timing, SDF, and ECO issues.
• Define and execute verification plans, regressions, and debugging across SoCs.

Skills

ASIC verification

SystemVerilog

UVM

RTL verification

Test benches

Debugging

Job description

Qualinx is seeking a Team Lead Digital ASIC Verification Engineer to shape the verification strategy for our next-generation SoCs. You will verify digital IP blocks, lead testbench creation, and collaborate with backend teams on timing and ECO issues.

The role emphasizes leading verification efforts, building robust environments, and ensuring high-quality digital designs through SystemVerilog and UVM expertise.