Senior ASIC Digital Verification Architect (Security IP)

Synopsys Inc; Eindhoven; On-site; EUR 75,000 - 120,000; Full time

Job summary

Synopsys Eindhoven seeks an experienced verification expert to design and execute verification strategies for security IP subsystems. You will build UVM testbenches, apply formal methods, and develop coverage models tied to product requirements.

The role involves automating regression, debugging RTL/testbench, and validating hardware/software integration on FPGA and simulators. You will join the Eindhoven Security IP team, collaborating with HW/SW engineers to protect devices across automotive,

Qualifications

• 6+ years hands-on verification experience in digital hardware IP.
• Proven track record verifying IP through multiple tape-outs or product releases.
• Deep expertise in SystemVerilog, UVM, assertion-based verification, and formal verification.
• Strong understanding of IC design flows and RTL handoff to implementation.

Responsibilities

• Design and execute verification strategies for security IP subsystems with digital components.
• Build and maintain UVM testbenches and formal verification flows for IP subsystems.
• Develop test plans, specifications, and coverage models aligned to product requirements.
• Automate regression environments using scripting to enable continuous verification.
• Run verification tests in simulators and on FPGA platforms.
• Debug RTL and testbench issues, root-cause defects with design teams.
• Apply formal verification to prove properties and corner cases.
• Support embedded software and driver verification for hardware/software integration.

Skills

SystemVerilog

UVM

Assertion-based verification

Coverage-driven methodology

Formal verification techniques

RTL design principles

Scripting (Python)

Scripting (Perl)

Scripting (TCL)

Education

Bachelor’s or Master’s degree in Electrical Engineering or Computer Science

Tools

Python

Perl

TCL

Job description

Synopsys Eindhoven seeks an experienced verification expert to design and execute verification strategies for security IP subsystems. You will build UVM testbenches, apply formal methods, and develop coverage models tied to product requirements.

The role involves automating regression, debugging RTL/testbench, and validating hardware/software integration on FPGA and simulators. You will join the Eindhoven Security IP team, collaborating with HW/SW engineers to protect devices across automotive,