FPGA Design Engineer

ASML; Veldhoven; On-site; EUR 70,000 - 110,000; Full time

Job summary

ASML Holding in the Netherlands seeks an FPGA Design Engineer to specify and design FPGA RTL blocks (IP) for data handling in a complex network. You will work with multidisciplinary teams spanning hardware, software and system architecture to deliver reliable RTL solutions from requirements through integration.

You should have 3+ years in FPGA or digital RTL design, strong SystemVerilog skills, and experience with Linux, Git and Python. English communication is essential.

Qualifications

• Three or more years of experience in FPGA or digital RTL design.
• Strong hands-on experience designing synthesizable RTL in SystemVerilog, including the use of SystemVerilog interfaces.
• Experience developing FPGA RTL designs from requirements and architecture through implementation and integration.
• Good understanding of synchronous digital design, including clocking, resets, FPGA primitives, timing and FSM design.
• Experience with FPGA simulation, linting, clock-domain crossing analysis, synthesis, implementation and timing analysis toolchains.
• Experience with digital communication, synchronization, networking or similar data-processing applications.
• Experience with Linux, Git, Python and C.
• Strong written and verbal communication skills in English.

Responsibilities

• Translate requirements into reliable and maintainable FPGA RTL blocks.
• Make design choices affecting development effort, performance and maintainability.
• Design RTL blocks in SystemVerilog with robust reset handling and clock-domain crossing awareness.
• Document RTL architecture, behavior and decisions; flag interface inconsistencies early.
• Collaborate with verification engineers, FPGA designers and software teams on issues.
• Develop and execute hardware tests for requirements not covered by simulation-based verification.
• Create effort estimates and adapt to changing requirements.
• Contribute to technical roadmaps and development practices.

Skills

SystemVerilog

RTL design

Digital design

Linux

Git

Python

C

English

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

SystemVerilog interfaces

FPGA toolchains

Job description

Introduction to the job

As an FPGA Design Engineer, you will specify and design FPGA RTL blocks (IP) for data handling and synchronization in a complex communication network. These blocks are primarily developed in SystemVerilog and combined with other RTL blocks to create a complete FPGA system.

You will work in a multidisciplinary engineering team alongside FPGA designers, FPGA verification engineers, software developers, hardware engineers and system architects. Your work will span RTL design, requirements definition, stakeholder management, RTL design documentation, team alignment, debugging and hardware validation.

Role and responsibilities

As an FPGA Design Engineer, you will translate requirements into reliable and maintainable FPGA RTL (IP) blocks. You will make design choices that affect development effort, performance, resource utilization, cost of goods, complexity and long-term maintainability.

You will:

• Design RTL blocks in SystemVerilog, including robust exception handling for reset behavior, incomplete transfers and notifications to higher-level software, while preventing clock-domain crossing issues.
• Define, document and negotiate requirements, including rationale, feasibility and verifiability.
• Analyze design alternatives, perform trade-off studies and align implementation decisions with stakeholders.
• Document RTL architecture, behavior and design decisions, and identify interface inconsistencies early.
• Collaborate with verification engineers, FPGA designers, software developers and integrators on block and system-level issues.
• Develop and execute hardware tests for requirements not covered by simulation-based verification.
• Create effort estimates with incomplete information and adapt to changing requirements.
• Contribute to technical roadmaps, FPGA development practices, product integration and technical issue resolution.

Education and experience

You have a bachelor's or master's degree in electrical engineering, computer engineering or a related technical field.

We are looking for candidates with:

• Three or more years of experience in FPGA or digital RTL design.
• Strong hands-on experience designing synthesizable RTL in SystemVerilog, including the use of SystemVerilog interfaces.
• Experience developing FPGA RTL designs from requirements and architecture through implementation and integration.
• A good understanding of synchronous digital design, including clocking, resets, FPGA primitives, timing and finite-state machine design.
• Experience with FPGA simulation, linting, clock-domain crossing analysis, synthesis, implementation and timing analysis toolchains.
• Experience with digital communication, synchronization, networking or comparable data-processing applications.
• Experience with Linux, Git, Python and C.
• Experience working in multidisciplinary engineering environments.
• Strong written and verbal communication skills in English.

Experience with high-speed digital interfaces or with developing reusable FPGA RTL is considered an advantage.

Skills

You enjoy solving complex digital design problems and are comfortable working across the boundary between architecture and implementation.

To thrive in this role, you will need:

• Strong analytical and problem-solving skills.
• The ability to translate complex requirements into clear, practical and maintainable RTL designs.
• A structured approach to digital design and technical problem-solving.
• The ability to reason about architectural and implementation trade-offs.
• Strong collaboration skills across hardware, software and system disciplines.
• The ability to prioritize tasks and work independently.
• Clear technical communication and documentation skills.
• A proactive approach to improving designs, methods and engineering practices.

Other information

You will join a multidisciplinary engineering team developing FPGA-based technology for complex, high-performance systems. The team develops reusable RTL blocks and works closely with hardware, software and system engineering teams from early architecture through product integration.

This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.

Inclusion and diversity

ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.