FPGA SystemVerilog RTL Design Engineer

ASML; Veldhoven; On-site; EUR 70,000 - 110,000; Full time

Job summary

ASML Holding in the Netherlands seeks an FPGA Design Engineer to specify and design FPGA RTL blocks (IP) for data handling in a complex network. You will work with multidisciplinary teams spanning hardware, software and system architecture to deliver reliable RTL solutions from requirements through integration.

You should have 3+ years in FPGA or digital RTL design, strong SystemVerilog skills, and experience with Linux, Git and Python. English communication is essential.

Qualifications

• Three or more years of experience in FPGA or digital RTL design.
• Strong hands-on experience designing synthesizable RTL in SystemVerilog, including the use of SystemVerilog interfaces.
• Experience developing FPGA RTL designs from requirements and architecture through implementation and integration.
• Good understanding of synchronous digital design, including clocking, resets, FPGA primitives, timing and FSM design.
• Experience with FPGA simulation, linting, clock-domain crossing analysis, synthesis, implementation and timing analysis toolchains.
• Experience with digital communication, synchronization, networking or similar data-processing applications.
• Experience with Linux, Git, Python and C.
• Strong written and verbal communication skills in English.

Responsibilities

• Translate requirements into reliable and maintainable FPGA RTL blocks.
• Make design choices affecting development effort, performance and maintainability.
• Design RTL blocks in SystemVerilog with robust reset handling and clock-domain crossing awareness.
• Document RTL architecture, behavior and decisions; flag interface inconsistencies early.
• Collaborate with verification engineers, FPGA designers and software teams on issues.
• Develop and execute hardware tests for requirements not covered by simulation-based verification.
• Create effort estimates and adapt to changing requirements.
• Contribute to technical roadmaps and development practices.

Skills

SystemVerilog

RTL design

Digital design

Linux

Git

Python

C

English

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

SystemVerilog interfaces

FPGA toolchains

Job description

ASML Holding in the Netherlands seeks an FPGA Design Engineer to specify and design FPGA RTL blocks (IP) for data handling in a complex network. You will work with multidisciplinary teams spanning hardware, software and system architecture to deliver reliable RTL solutions from requirements through integration.

You should have 3+ years in FPGA or digital RTL design, strong SystemVerilog skills, and experience with Linux, Git and Python. English communication is essential.