Test Engineer

Pride Global; Penang; On-site; MYR 120,000 - 240,000; Full time

Job summary

Pride Global in Penang, Malaysia is seeking an experienced Design for Test (DFT) Engineer to join our semiconductor design team. The role is onsite in Penang with permanent, full‑time employment and Malaysia work authorization required.

You will lead DFT architecture for ASIC/SoC, perform scan insertion and compression, and generate ATPG patterns. Collaboration with Physical Design, RTL, Verification and Product Engineering teams is essential to deliver robust silicon and optimize yield.

Qualifications

• 4–15 years of hands‑on ASIC/SoC DFT experience
• Strong experience in Scan & ATPG
• Hands‑on experience with Scan Insertion, Scan Compression, MBIST & LBIST
• Strong knowledge of JTAG (IEEE 1149.1) & IJTAG (IEEE 1687)
• Experience with DFT implementation & Test Architecture Development
• Good understanding of Verilog/SystemVerilog
• Scripting: Tcl / Python / Perl preferred

Responsibilities

• DFT architecture development for ASIC/SoC designs
• Scan insertion and compression
• ATPG pattern generation & debugging
• RTL and gate-level DFT verification
• Collaboration with Physical Design, RTL, Verification & Product Engineering teams
• Silicon debug, yield analysis & test optimization
• Manufacturing test readiness & silicon bring-up

Skills

DFT/ASIC/SoC

Scan & ATPG

Scan Insertion

Scan Compression

MBIST / LBIST

JTAG / IJTAG

Verilog/SystemVerilog

Scripting (Tcl/Python)

Education

Bachelor/Master in Electrical/ Electronics/ Computer Engineering or related field

Tools

Synopsys DFTMAX

Synopsys TetraMAX

Design Compiler

Fusion Compiler

Mentor Tessent

Mentor FastScan

Mentor TestKompress

Cadence Modus

Cadence Genus

Job description

HIRING | Design for Test (DFT) Engineer | Penang, Malaysia

We are looking for an experienced Design for Test (DFT) Engineer to join our semiconductor design team.

Location: Penang, Malaysia

Employment: Permanent | Full-Time

Work Mode: Onsite

Work Authorization: Malaysia Local / PR / RPT ONLY

KEY REQUIREMENTS

• 4–15 years of hands‑on ASIC/SoC DFT experience
• Strong experience in Scan & ATPG
• Hands‑on experience with Scan Insertion, Scan Compression, MBIST & LBIST
• Strong knowledge of JTAG (IEEE 1149.1) & IJTAG (IEEE 1687)
• Experience with DFT implementation & Test Architecture Development
• Good understanding of Verilog/SystemVerilog
• Scripting: Tcl / Python / Perl preferred

EXPERIENCE WITH ONE OR MORE DFT TOOL SUITES

• Synopsys – DFTMAX, TetraMAX, Design Compiler, Fusion Compiler
• Siemens/Mentor – Tessent, FastScan, TestKompress
• Cadence – Modus, Genus

ROLE FOCUS

• DFT architecture development for ASIC/SoC designs
• Scan insertion and compression
• ATPG pattern generation & debugging
• RTL and gate-level DFT verification
• Collaboration with Physical Design, RTL, Verification & Product Engineering teams
• Silicon debug, yield analysis & test optimization
• Manufacturing test readiness & silicon bring-up

Education: Bachelor's / Master's in Electrical, Electronics, Computer Engineering or related field.