DFT Engineer

Avensys Consulting; Kuala Lumpur; On-site; MYR 120,000 - 180,000; Full time

Job summary

Avensys is seeking a skilled DFT Engineer to design and implement DFT solutions for complex SoC/ASIC designs, working with Physical Design, Verification and other engineering teams. You will develop DFT architectures, generate test patterns and support silicon bring-up to ensure high test coverage and product quality.

The ideal candidate has 4+ years of hands-on DFT/VLSI experience, expertise in Scan Architecture, ATPG, and familiarity with Synopsys DFT Compiler.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics or a related field.
• 4+ years of hands-on experience in DFT / VLSI design.
• Strong practical experience with SoC/ASIC DFT implementation.
• Experience working with full-chip or block-level DFT flows.
• Hands-on experience with Synopsys DFT Compiler.
• Strong experience with Scan Architecture and Scan Insertion.
• Experience with ATPG and fault modeling.
• Good understanding of test compression techniques.
• Experience with Boundary Scan (JTAG) implementation.
• Good understanding of digital design fundamentals.
• Solid understanding of timing and physical design constraints related to DFT.
• Experience supporting DFT activities through pre-silicon and post-silicon validation.
• Experience with Tcl and/or Python scripting is an added advantage.
• Exposure to advanced process nodes is a plus.

Responsibilities

• Design and implement DFT architectures for complex SoC/ASIC designs, including: Scan insertion
• MBIST (Memory Built-In Self-Test) and LBIST (Logic Built-In Self-Test)
• Perform ATPG and analyze test coverage
• Implement and optimize test compression techniques to improve efficiency
• Debug DFT-related issues during pre-silicon and post-silicon stages
• Support silicon bring-up and validation activities
• Work with Design Verification and Physical Design teams for DFT closure
• Ensure DFT implementations comply with methodologies and quality standards
• Analyze test coverage reports to identify gaps and improvements
• Troubleshoot DFT-related production test issues
• Support production test readiness and DFT process improvements

Skills

DFT architecture

Scan insertion

MBIST

LBIST

ATPG

test compression

JTAG

timing constraints

Scripting (Tcl/Python)

Education

Electrical Engineering

Electronics Engineering

VLSI

Microelectronics

Tools

Synopsys DFT Compiler

Job description

Avensys is a reputed global IT professional services company headquartered in Singapore. Our service spectrum includes enterprise solution consulting, business intelligence, business process automation and managed services. Given our decade of success we have evolved to become one of the top trusted providers in Singapore and service a client base across banking and financial services, insurance, information technology, healthcare, retail and supply chain.

Type: Permanent Role

We are looking for a skilled DFT Engineer to design and implement Design for Testability (DFT) solutions for complex SoC/ASIC designs. The role involves developing and integrating DFT architectures, generating test patterns, supporting silicon bring-up, and ensuring comprehensive test coverage and product quality.

The successful candidate will work closely with Physical Design, Verification, and other engineering teams throughout the pre-silicon and post-silicon stages.

Key Responsibilities

The successful candidate will:

• Design and implement DFT architectures for complex SoC/ASIC designs, including:Scan insertion
• MBIST (Memory Built-In Self-Test)
• LBIST (Logic Built-In Self-Test)

Perform ATPG (Automatic Test Pattern Generation) and analyze test coverage.

Implement and optimize test compression techniques to improve test efficiency and reduce test time.

Debug DFT-related issues during both pre-silicon and post-silicon stages.

Support silicon bring-up and validation activities.

Work closely with cross-functional engineering teams, including:

• Design Verification teams for DFT validation
• Physical Design / Backend teams for DFT implementation and closure

Ensure DFT implementation complies with established DFT methodologies, design requirements, and quality standards.

Analyze test coverage reports and identify coverage gaps, testability issues, and potential improvements.

Troubleshoot and resolve DFT-related implementation and production test issues.

• Support production test readiness and contribute to continuous improvement of DFT methodologies and processes.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related field.

4+ years of hands-on experience in DFT / VLSI design.

Strong practical experience with SoC/ASIC DFT implementation.

Experience working with full-chip or block-level DFT flows.

Hands-on experience with Synopsys DFT Compiler.

Strong experience with Scan Architecture and Scan Insertion.

Experience with ATPG and fault modeling.

Good understanding of test compression techniques.

Experience with Boundary Scan (JTAG) implementation.

Good understanding of digital design fundamentals.

Solid understanding of timing and physical design constraints related to DFT.

Experience supporting DFT activities through pre-silicon and post-silicon validation.

Experience with Tcl and/or Python scripting is an added advantage.

Exposure to advanced process nodes is a plus.

WHAT’S ON OFFER:

You will be remunerated with an excellent base salary and entitled to attractive company benefits. Additionally, you will get the opportunity to enjoy a fun and collaborative work environment, alongside a strong career progression.

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