Technical Manager, Digital Physical Design

4ASICS TECHNOLOGY SDN BHD; Penang; On-site; MYR 180,000 - 360,000; Full time

Job summary

4ASICs in Penang is seeking a Physical Design Technical Manager to build and lead a new PD team. This hands-on leader will drive end-to-end PD flows from synthesis to GDSII sign-off across multiple projects, including advanced TSMC FinFET nodes.

You will mentor engineers, define EDA methodologies, and collaborate with international customers on tape-outs and pre-sales activities, working closely with RTL/STA/DFT teams to ensure quality, schedules and successful deliveries.

Qualifications

• Education: Bachelor's or Master's in Electrical/Electronics or related.
• At least 8 years of hands-on Digital Physical Design experience with tape-outs.
• Experience with TSMC FinFET nodes from 16nm to 3nm or smaller.
• Strong RTL-to-GDSII knowledge: floorplanning, power, CTS, routing, timing closure, EM/IR drop.
• Proven leadership and mentoring ability; strong communication with international customers.
• Proficiency in Linux and scripting (Tcl, Python, Perl, shell).

Responsibilities

• Lead Digital Physical Design implementation from synthesized netlist through GDSII signoff across multiple projects.
• Drive floorplanning, power planning, placement, CTS, routing, timing closure, power optimization, signal integrity, IR drop, EM, and physical verification.
• Recruit, mentor, and develop a high-performing Physical Design team with training plans and reviews.
• Define and automate Physical Design methodologies and EDA flows using Tcl, Python or similar.
• Serve as the primary technical interface for international customers, lead design reviews, ensure project quality, schedule and delivery.
• Provide technical input for customer discussions, project scoping, proposals, and pre-sales activities.
• Collaborate with RTL, STA, DFT, Verification, and Analog/Mixed-Signal teams to resolve design issues and tape-outs.

Skills

Hands-on leadership

RTL-to-GDSII implementation

Floorplanning

Power planning

Placement & Routing

Timing closure

DRC/LVS

Signal integrity

EM

Scripting (Tcl/Python/Perl)

Linux

Communication in English

Education

Bachelor's or Master's in Electrical/Electronics or related

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Synopsys ICC2

Fusion Compiler

PrimeTime

Siemens Calibre

Job description

4ASICs in Penang is seeking a Physical Design Technical Manager to build and lead a new PD team. This hands-on leader will drive end-to-end PD flows from synthesis to GDSII sign-off across multiple projects, including advanced TSMC FinFET nodes.

You will mentor engineers, define EDA methodologies, and collaborate with international customers on tape-outs and pre-sales activities, working closely with RTL/STA/DFT teams to ensure quality, schedules and successful deliveries.