STA Engineer - Synthesis

Pride Global; Seberang Perai; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global in Malaysia is seeking an experienced Synthesis & STA Engineer to support ASIC/SoC design projects. The role focuses on RTL synthesis, static timing analysis, timing closure, and design optimization to meet PPA objectives.

You will collaborate with RTL, Physical Design, and DFT teams to identify timing issues, optimize performance, and ensure timing requirements across the design flow. Strong Verilog/SystemVerilog and TCL scripting are essential, with experience in Synopsys tools

Qualifications

• Bachelor's or Master's degree in Electrical or related field.
• 4-10 years in ASIC/SoC design, RTL synthesis or STA.
• Strong hands-on RTL synthesis and STA methods.
• Proficient in Verilog/SystemVerilog and digital design fundamentals.
• Experience with Synopsys tools and timing constraints.

Responsibilities

• Perform RTL synthesis to create optimized gate-level netlists.
• Develop and optimize synthesis scripts and timing constraints.
• Conduct STA including setup/hold/recovery checks and timing reports.
• Identify critical paths and timing violations; propose fixes.
• Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
• Create and maintain SDC files for accurate timing analysis.
• Optimize designs to meet frequency, power, and area targets.
• Support timing closure across pre-layout and post-layout stages.
• Analyze clock domains, false paths, multicycle paths, and CDC issues.
• Assist timing signoff and use EDA tools to improve timing performance.
• Help engineering teams identify optimization opportunities in the ASIC/SoC flow.

Skills

RTL synthesis

Static timing analysis

Verilog/SystemVerilog

Tcl scripting

Debugging / problem solving

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

PrimeTime

SDC (constraints)

Job description

Employment type : Open to Perm & Contract

Working arrangement : Onsite

Salary Range : 4-6 Years (11-12k), 6-8 Years (13-15k), 8-10 Years (16-18k)

Job Summary

We are seeking an experienced Synthesis & Static Timing Analysis (STA) Engineer to support ASIC and System-on-Chip (SoC) design projects. The successful candidate will be responsible for RTL synthesis, static timing analysis, timing closure, and design optimization to achieve power, performance, and area (PPA) objectives.

The role involves working closely with RTL design, Physical Design, and Design-for-Test (DFT) teams to identify and resolve timing issues, optimize design performance, and ensure compliance with timing requirements throughout the semiconductor design flow.

Key Responsibilities

• Perform RTL synthesis to transform RTL designs into optimized gate-level netlists.
• Develop, maintain, and optimize synthesis scripts, timing constraints, and design configurations.
• Conduct Static Timing Analysis (STA), including setup, hold, recovery, and removal checks.
• Analyze timing reports to identify critical paths, timing violations, and potential design bottlenecks.
• Collaborate with RTL, Physical Design, and DFT teams to troubleshoot and resolve timing-related issues.
• Develop, validate, and maintain Synopsys Design Constraints (SDC) for accurate timing analysis.
• Optimize design implementations to meet frequency, power, and area (PPA) targets.
• Support timing closure activities across various design stages, including pre-layout and post-layout analysis.
• Analyze and resolve timing constraint issues involving clocks, false paths, multicycle paths, and clock domain crossings (CDC), where applicable.
• Support timing signoff activities to ensure all design timing requirements are satisfied.
• Utilize Electronic Design Automation (EDA) tools to debug design issues, improve timing performance, and enhance overall design quality.
• Support engineering teams in identifying optimization opportunities and improving the efficiency of the ASIC/SoC design flow.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, or a related discipline.
• 4-10 years of relevant experience in ASIC/SoC design, RTL synthesis, or Static Timing Analysis.
• Strong hands-on experience in RTL synthesis and STA methodologies.
• Good understanding of Verilog/SystemVerilog, digital logic design, and semiconductor design fundamentals.
• Practical experience with Synopsys Design Compiler, Fusion Compiler, PrimeTime, or equivalent EDA tools.
• Strong knowledge of timing constraints, SDC, setup and hold analysis, and timing report interpretation.
• Proficiency in Tcl scripting; experience with Perl or Python is an advantage.
• Understanding of CMOS technology, standard-cell libraries, and semiconductor design flows.
• Strong analytical, debugging, and problem-solving skills.
• Ability to collaborate effectively with cross-functional engineering teams.

Preferred Qualifications

• Experience working with advanced semiconductor technology nodes, including 10nm, 7nm, 5nm, or below.
• Knowledge of low-power design methodologies and PPA optimization techniques.
• Hands-on experience with post-layout STA, parasitic extraction, and timing signoff.
• Familiarity with PrimeTime SI, Engineering Change Order (ECO) implementation, and Multi-Corner Multi-Mode (MCMM) analysis.
• Experience supporting complex ASIC/SoC projects and achieving timing closure in advanced technology environments.