Senior SoC Timing Closure Expert

UST Malaysia

Penang

In loco

MYR 180.000 - 300.000

Tempo pieno

4 giorni fa

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Descrizione del lavoro

UST Malaysia is seeking a Senior STA Engineer with 8+ years in ASIC/SoC timing closure to drive timing convergence from synthesis through signoff for high-performance silicon. You will collaborate with RTL, physical design, DFT, and design teams to ensure robust timing across modes and corners, including SI and cross-talk analysis.

The role requires strong experience with STA fundamentals, SDC, CDC, and advanced nodes, plus scripting skills in TCL/Perl/Python for automation.

Competenze

8+ years of experience in ASIC/SoC STA and timing closure.
Strong understanding of STA fundamentals and timing constraints.
Experience with advanced technology nodes (16nm and below preferred).

Mansioni

Perform block-level and full-chip STA, timing analysis, and signoff.
Drive setup/hold closure across all modes and corners.
Develop and validate timing constraints (SDC) and timing exceptions.
Analyze and resolve timing violations related to clocks, data paths, and interfaces.
Work closely with RTL, PD, DFT, and design teams to achieve timing closure.
Support ECO implementation and timing verification.
Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
Debug timing issues and provide optimization recommendations for PPA improvements.
Support tapeout activities and signoff readiness.