Senior STA Engineer: Drive Timing Closure for ASIC/SoC

UST Malaysia; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

UST Malaysia is seeking a Senior Static Timing Analysis Engineer in Penang to lead timing convergence from synthesis through signoff, ensuring high-performance and low-power silicon delivery. The role requires 8+ years of ASIC/SoC STA experience and deep knowledge of timing constraints, CDC, and signoff methodologies.

You will collaborate with RTL, Physical Design, DFT, and Design teams to close timing across modes and corners, support ECOs, and participate in tapeout readiness.

Qualifications

• BS/Master in EE/EC or CS with emphasis on timing.
• 8+ years of ASIC/SoC STA and timing closure experience.
• Familiarity with advanced technology nodes (16nm and below preferred).

Responsibilities

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Skills

Static Timing Analysis

Timing debugging

Scripting (Tcl/Python)

Clock Domain Crossing

Problem solving

Education

Bachelor’s or Master’s in Electrical/Electronics/Computer Engineering

Tools

Tempus

Job description

UST Malaysia is seeking a Senior Static Timing Analysis Engineer in Penang to lead timing convergence from synthesis through signoff, ensuring high-performance and low-power silicon delivery. The role requires 8+ years of ASIC/SoC STA experience and deep knowledge of timing constraints, CDC, and signoff methodologies.

You will collaborate with RTL, Physical Design, DFT, and Design teams to close timing across modes and corners, support ECOs, and participate in tapeout readiness.