Synthesis & STA Engineer - Timings & PPA Optimizer (Onsite)

Pride Global; Penang; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global is seeking an experienced STA Engineer to support ASIC and SoC synthesis and timing analysis projects in Bayan Lepas, Penang. You will work with RTL design, Physical Design, and DFT teams to ensure timing closure and PPA targets.

The role focuses on RTL synthesis, STA, timing constraints, and design optimization to meet power, performance, and area goals. Onsite role with 4–10 years of relevant experience and hands-on tool proficiency.

Qualifications

• 4–10 years of ASIC/SoC design, RTL synthesis, or STA experience.
• Strong experience with Verilog/SystemVerilog and digital logic fundamentals.
• Proficiency in Tcl scripting; Perl or Python a plus.
• Experience with Synopsys tools: Design Compiler, Fusion Compiler, PrimeTime.

Responsibilities

• Perform RTL synthesis to transform RTL designs into optimized gate-level netlists.
• Develop, maintain, and optimize synthesis scripts, timing constraints, and design configurations.
• Conduct Static Timing Analysis (STA), including setup, hold, recovery, and removal checks.
• Analyze timing reports to identify critical paths, timing violations, and potential design bottlenecks.
• Collaborate with RTL, Physical Design, and DFT teams to troubleshoot and resolve timing-related issues.
• Develop, validate, and maintain SDCs for accurate timing analysis.
• Optimize design implementations to meet frequency, power, and area targets.
• Support timing closure activities across pre-layout and post-layout stages.
• Analyze timing constraint issues involving clocks, false paths, CDC as applicable.
• Support timing signoff activities to ensure all design timing requirements.

Skills

RTL synthesis

STA

Verilog/SystemVerilog

Tcl scripting

Cross-functional

Education

Bachelor's or Master's in Electrical Engineering

Tools

Design Compiler

Fusion Compiler

PrimeTime

Job description

Pride Global is seeking an experienced STA Engineer to support ASIC and SoC synthesis and timing analysis projects in Bayan Lepas, Penang. You will work with RTL design, Physical Design, and DFT teams to ensure timing closure and PPA targets.

The role focuses on RTL synthesis, STA, timing constraints, and design optimization to meet power, performance, and area goals. Onsite role with 4–10 years of relevant experience and hands-on tool proficiency.