Senior STA Engineer

UST Malaysia; George Town; In loco; MYR 180.000 - 300.000; Tempo pieno

Descrizione del lavoro

UST Malaysia is seeking a Senior Static Timing Analysis Engineer in Penang to lead timing convergence from synthesis through signoff, ensuring high-performance and low-power silicon delivery. The role requires 8+ years of ASIC/SoC STA experience and deep knowledge of timing constraints, CDC, and signoff methodologies.

You will collaborate with RTL, Physical Design, DFT, and Design teams to close timing across modes and corners, support ECOs, and participate in tapeout readiness.

Competenze

• BS/Master in EE/EC or CS with emphasis on timing.
• 8+ years of ASIC/SoC STA and timing closure experience.
• Familiarity with advanced technology nodes (16nm and below preferred).

Mansioni

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Conoscenze

Static Timing Analysis

Timing debugging

Scripting (Tcl/Python)

Clock Domain Crossing

Problem solving

Formazione

Bachelor’s or Master’s in Electrical/Electronics/Computer Engineering

Strumenti

Tempus

Descrizione del lavoro

We are seeking a Senior Static Timing Analysis (STA) Engineer with 8+ years of experience in ASIC/SoC timing closure. The candidate will be responsible for driving timing convergence from synthesis through signoff, ensuring high-performance and low-power silicon delivery across advanced technology nodes.

Key Responsibilities

• Perform block-level and full-chip STA, timing analysis, and signoff.
• Drive setup/hold closure across all modes and corners.
• Develop and validate timing constraints (SDC) and timing exceptions.
• Analyze and resolve timing violations related to clocks, data paths, and interfaces.
• Work closely with RTL, Physical Design, DFT, and Design teams to achieve timing closure.
• Support ECO implementation and timing verification.
• Perform timing signoff checks including SI, OCV/AOCV/POCV, crosstalk, and noise analysis.
• Debug timing issues and provide optimization recommendations for PPA improvements.
• Support tapeout activities and signoff readiness.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 6+ years of experience in ASIC/SoC STA and timing closure.
• Strong understanding of:
• Static Timing Analysis fundamentals
• Timing Constraints (SDC)
• Clock Domain Crossing (CDC)
• OCV/AOCV/POCV methodologies
• Crosstalk and Signal Integrity analysis
• MCMM timing analysis
• Hands-on experience with:
• Tempus (preferred)
• Experience with advanced technology nodes (16nm and below preferred).
• Proficiency in Tcl, Perl, or Python scripting.

Preferred Qualifications

• Experience with full-chip signoff and tapeout.
• Knowledge of Physical Design flow and ECO methodologies.
• Familiarity with low-power designs (UPF/CPF).
• Experience in 7nm, 5nm, or advanced FinFET technologies.

Key Skills

• Strong timing debugging and analysis skills.
• Excellent problem-solving and analytical abilities.
• Ability to work independently and drive timing closure.
• Effective communication and cross-functional collaboration.