SoC Physical Design Engineer — PnR & Timing Expert

Uni Connect; Bayan Lepas; On-site; MYR 60,000 - 80,000; Full time

Job summary

A technology design company in Bayan Lepas is looking for an experienced engineer to participate in cutting-edge System-On-a-Chip (SoC) design projects. The ideal candidate possesses a Bachelor’s degree in electrical engineering and has strong understanding of digital logic and Verilog. Responsibilities include executing physical design flows and improving methodologies within aggressive schedules. Familiarity with Synopsys and Cadence EDA tools is essential. Competitive salary and growth opportunities are offered.

Qualifications

• Strong understanding of digital logic, VHDL/RTL representations, and Verilog.
• Experience with Synopsys EDA tools, including Fusion Compiler, PrimeTime.
• Hands-on experience with place‑and‑route (PnR), physical verification, timing convergence.

Responsibilities

• Participate in SoC design projects using cutting-edge technology.
• Execute complete physical design flow from RTL to GDS.
• Work as part of a team both locally and with remote teams.

Skills

Digital logic understanding

VHDL/RTL representations

Verilog proficiency

Perl programming

TCL scripting

Python for CAD automation

Education

Bachelor’s degree in electrical engineering or related discipline

Tools

Synopsys EDA tools

Cadence EDA tools

Job description

A technology design company in Bayan Lepas is looking for an experienced engineer to participate in cutting-edge System-On-a-Chip (SoC) design projects. The ideal candidate possesses a Bachelor’s degree in electrical engineering and has strong understanding of digital logic and Verilog. Responsibilities include executing physical design flows and improving methodologies within aggressive schedules. Familiarity with Synopsys and Cadence EDA tools is essential. Competitive salary and growth opportunities are offered.