Senior Verification Engineer, FPGA/ASIC & SystemVerilog

Oppstar Berhad; Penang; On-site; MYR 120,000 - 170,000; Full time

Job summary

Oppstar Berhad is seeking an experienced verification engineer for pre-Si verification of FPGA/ASIC designs. The role involves test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regressions to ensure high-quality designs.

Candidate will collaborate with product/IP architects, logic design engineers, DFX owners, and design automation engineers to ensure robust design validation across IP blocks and full-chip implementations.

Job description

Oppstar Berhad is seeking an experienced verification engineer for pre-Si verification of FPGA/ASIC designs. The role involves test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regressions to ensure high-quality designs.

Candidate will collaborate with product/IP architects, logic design engineers, DFX owners, and design automation engineers to ensure robust design validation across IP blocks and full-chip implementations.