Senior USB IP Verification Engineer - Hybrid Role

Intel Corporation; Malaysia; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

Intel Corporation is seeking an experienced Senior USB IP Design Verification Engineer in Malaysia (Penang/Kulim). You will verify USB IP designs, develop testbenches, and drive coverage and bug fixes across pre-silicon stages. Collaboration with architects, RTL teams, and physical design is essential.

Hybrid work model in Malaysia is available. The role requires 6–8 years of RTL verification experience, strong SystemVerilog/UVM skills, and exposure to VCS or similar tools.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or equivalent.
• 6–8 years of RTL design verification experience.
• Proficiency in SystemVerilog and UVM/OVM methodologies.
• Familiarity with pre-silicon verification tools such as VCS/Synopsys.
• Knowledge of USB, PCIe, or AMBA protocols.

Responsibilities

• Develop functional verification plans and testbenches for microarchitecture specifications.
• Execute verification strategies via system simulations, analyzing power, timing and functionality.
• Debug and fix failing tests in presilicon environments.
• Collaborate with architects, RTL developers and physical design teams.
• Maintain and improve verification infrastructure and methodologies.
• Document test plans and lead technical reviews.

Skills

SystemVerilog

UVM/OVM

Testbench

Coverage points

Assertions

Python

VCS

Pre-silicon

USB/PCIe/AMBA

High-speed IO

Education

Bachelor's degree in Electrical/Computer Engineering

Job description

Intel Corporation is seeking an experienced Senior USB IP Design Verification Engineer in Malaysia (Penang/Kulim). You will verify USB IP designs, develop testbenches, and drive coverage and bug fixes across pre-silicon stages. Collaboration with architects, RTL teams, and physical design is essential.

Hybrid work model in Malaysia is available. The role requires 6–8 years of RTL verification experience, strong SystemVerilog/UVM skills, and exposure to VCS or similar tools.