Senior USB IP Design Verification Engineer

Intel; Kulim; Hybrid; MYR 120,000 - 180,000; Full time

Job summary

Intel in Malaysia is seeking an IP Design Verification Engineer to verify USB/IP designs, develop test plans, and collaborate with RTL, architecture and physical design teams to ensure quality and performance across products.

The role focuses on pre-silicon verification, system-level simulations, coverage, and debugging, with a hybrid work model and opportunities to influence next-generation silicon technologies.

Qualifications

• Bachelor's degree in a relevant engineering or computer science field.
• 6–8 years of RTL design verification experience with SystemVerilog and UVM/OVM.
• Experience designing test plans and testbench infrastructure with monitors, scoreboards, BFMs, and coverage points.
• Familiarity with pre-silicon verification tools and scripting for automation (Python/Perl/Shell).
• Understanding of high-speed IPs (USB, PCIe, AMBA) and VLSI design flows.

Responsibilities

• Develop functional verification plans and test benches for microarchitecture specs.
• Execute verification strategies using system simulations to analyze power, timing, and functionality.
• Address failing tests and debug issues in pre-silicon environments.
• Collaborate with architects, RTL developers, and physical design teams to validate features.
• Maintain and improve verification infrastructure and methodologies.
• Document test plans and lead technical reviews with design teams.
• Improve test coverage, efficiency, and validation through innovative approaches.

Skills

RTL design verification

SystemVerilog

UVM/OVM methodologies

test plans & testbenches

pre-silicon verification tools

Education

Bachelor's degree in Electrical, Electronics, Computer Engineering, CS

Tools

VCS

Synopsys

Job description

Job Details

Job Description:

The Role and Impact

As an IP Design Verification Engineer, you will play a critical role in ensuring the functionality, quality, and efficiency of Intel's cutting‑edge USB IP designs. Working within a fast‑paced and innovative environment, you will be responsible for verifying IP logic to meet architectural specifications and standards, shaping the future of Intel's technology portfolio. Your efforts will directly impact the reliability and performance of products used globally, contributing to Intel's mission to create world‑changing technology that improves the lives of every person on the planet.

Key Responsibilities

• Develop functional verification plans and test benches to ensure comprehensive coverage of microarchitecture specifications.
• Execute verification strategies through system simulation models to analyze power, timing, and functionality while identifying and resolving bugs.
• Implement corrective measures to address failing tests and debug issues in the pre‑silicon environment.
• Collaborate with architects, RTL developers, and physical design teams to validate complex architectural and micro‑architectural features.
• Maintain and improve functional verification infrastructure and methodologies to support ongoing innovation.
• Document test plans and lead technical reviews with design and architecture teams to ensure alignment with project goals.
• Drive improvements in test coverage, efficiency, and execution time through innovative problem‑solving and validation techniques.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or equivalent.
• At least 6‑8 years of industry experience in RTL design verification with expertise in System Verilog and UVM/OVM methodologies.
• Proficiency in designing test plans, developing testbench infrastructure (including monitors, scoreboards, BFMs), and creating coverage points and assertion checks.
• Familiarity with pre‑silicon verification tools such as VCS/Synopsys and scripting languages like Python, Perl, or Shell for automation.
• Understanding of high‑speed IO IPs such as USB, PCI Express, or AMBA protocols.
• Comprehensive knowledge of VLSI design flows, structural and physical design methodologies, and power‑aware simulation techniques.

Preferred Qualifications

• Advanced degree in a relevant field (Master's or PhD).
• Experience with SoC‑level validation environments and subsystem interoperability validation.
• Expertise in power‑aware design, simulation, and validation flows for low‑power architecture.
• Strong analytical and debugging skills with a demonstrated ability to solve complex technical challenges.
• Prior experience in collaborating within diverse, cross‑functional teams to achieve project milestones.
• Effective communication, initiative, and adaptability to dynamic, fast‑evolving environments.

Join Intel and drive innovation that shapes the future of technology. Apply now to become part of a team where your expertise will make a meaningful impact.

Job Type

Experienced Hire

Shift

Shift 1 (Malaysia)

Primary Location

Malaysia, Penang

Additional Locations

Malaysia, Kulim

Business Group

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry‑leading products today while also defining the next generation of computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.