Senior USB IP Verification Engineer – Hybrid

Intel Corporation; Kulim; Hybrid; MYR 240,000 - 420,000; Full time

Job summary

Intel Corporation in Malaysia is seeking an IP Design Verification Engineer to ensure USB IP designs meet architectural specs. You will develop verification plans, build testbenches, and execute strategies across system simulations, collaborating with architects, RTL teams and physical design to validate complex features.

The role requires 6–8 years in RTL verification, SystemVerilog/UVM, and experience with pre-silicon tools.

Qualifications

• Bachelor’s degree in Electrical, Electronics, Computer Engineering or Computer Science.
• 6–8 years of RTL design verification with SystemVerilog and UVM/OVM.
• Experience designing test plans and testbench infrastructure (monitors, scoreboards, BFMs).
• Familiarity with pre-silicon verification tools (VCS/Synopsys) and scripting (Python/Perl/Shell).
• Knowledge of high-speed IO IPs such as USB, PCIe or AMBA.
• Understanding of VLSI design flows and power-aware simulation.

Responsibilities

• Develop functional verification plans and testbenches for microarchitecture specs.
• Execute verification strategies using system simulators to analyze power, timing and functionality.
• Address failing tests and debug issues in pre-silicon environment.
• Collaborate with architects, RTL developers and physical design teams to validate features.
• Maintain and improve verification infrastructure and methodologies.
• Document test plans and lead technical reviews with design and architecture teams.
• Improve test coverage and efficiency of verification processes.

Skills

Analytical skills

Debugging

Cross-functional collaboration

Communication

Education

Bachelor's degree in Electrical/ Electronics/ Computer Engineering or Computer Science

Master's degree or PhD preferred

Tools

SystemVerilog

UVM/OVM

VCS/Synopsys

Python

Perl

Shell scripting

Job description

Intel Corporation in Malaysia is seeking an IP Design Verification Engineer to ensure USB IP designs meet architectural specs. You will develop verification plans, build testbenches, and execute strategies across system simulations, collaborating with architects, RTL teams and physical design to validate complex features.

The role requires 6–8 years in RTL verification, SystemVerilog/UVM, and experience with pre-silicon tools.