USB IP Verification Engineer – Hybrid Role

Intel Corporation; Penang; Hybrid; MYR 78,000 - 100,000; Full time

Job summary

Intel Corporation in Malaysia, Penang, is seeking a passionate Verification Engineer to define a robust test coverage plan for USB IP validation across client products. You will scope validation plans, develop test contents and assertion checks, and build testbench infrastructure to close coverage while optimizing test efficiency.

The role targets college graduates with 0–1 year RTL verification exposure, familiar with SystemVerilog and RTL languages, and eager to learn in a hybrid work setup.

Qualifications

• Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, or a related field.
• 0-1 years of hands-on experience in RTL design verification from internships or coursework.
• Familiarity with SystemVerilog for design verification; basic Verilog/VHDL knowledge.
• Strong analytical and debugging skills, and creative problem solving.

Responsibilities

• Scoping and development of validation test plans for new architectural features and next generations USB IP development.
• Developing test contents, coverage points and assertion checks.
• Developing testbench infrastructure (monitors, scoreboards/checks, BFMs, etc) to close on validation coverage.
• Finding and implementing correct measure for failing tests.
• Continue to strive for innovation in problem-solving to improve test coverage and efficiency.
• Understanding SoC/Subsystem validation environment, and providing IP validation support.

Skills

SystemVerilog

Verilog

VHDL

Analytical skills

Debugging

Communication

Collaboration

Initiative

Education

Bachelor's degree in Electrical/Elect Electronics Engineering or related

Tools

OVM/UVM

GitHub Copilot

ChatGPT

Job description

Intel Corporation in Malaysia, Penang, is seeking a passionate Verification Engineer to define a robust test coverage plan for USB IP validation across client products. You will scope validation plans, develop test contents and assertion checks, and build testbench infrastructure to close coverage while optimizing test efficiency.

The role targets college graduates with 0–1 year RTL verification exposure, familiar with SystemVerilog and RTL languages, and eager to learn in a hybrid work setup.