USB IP Design Verification Engineer

Intel Corporation; Penang; Hybrid; MYR 78,000 - 100,000; Full time

Job summary

Intel Corporation in Malaysia, Penang, is seeking a passionate Verification Engineer to define a robust test coverage plan for USB IP validation across client products. You will scope validation plans, develop test contents and assertion checks, and build testbench infrastructure to close coverage while optimizing test efficiency.

The role targets college graduates with 0–1 year RTL verification exposure, familiar with SystemVerilog and RTL languages, and eager to learn in a hybrid work setup.

Qualifications

• Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, or a related field.
• 0-1 years of hands-on experience in RTL design verification from internships or coursework.
• Familiarity with SystemVerilog for design verification; basic Verilog/VHDL knowledge.
• Strong analytical and debugging skills, and creative problem solving.

Responsibilities

• Scoping and development of validation test plans for new architectural features and next generations USB IP development.
• Developing test contents, coverage points and assertion checks.
• Developing testbench infrastructure (monitors, scoreboards/checks, BFMs, etc) to close on validation coverage.
• Finding and implementing correct measure for failing tests.
• Continue to strive for innovation in problem-solving to improve test coverage and efficiency.
• Understanding SoC/Subsystem validation environment, and providing IP validation support.

Skills

SystemVerilog

Verilog

VHDL

Analytical skills

Debugging

Communication

Collaboration

Initiative

Education

Bachelor's degree in Electrical/Elect Electronics Engineering or related

Tools

OVM/UVM

GitHub Copilot

ChatGPT

Job description

Job Description

Passionate IP design Verification Engineer who is motivated to work on fast moving USB IP development across various Client products. The engineer will have an opportunity to define a robust and high-quality test coverage plan to validate new generations of USB IP and challenging new architectural features.

The responsibilities cover:

• Scoping and development of validation test plans for new architectural features and next generations USB IP development.
• Developing test contents, coverage points and assertion checks.
• Developing testbench infrastructure (monitors, scoreboards/checks, BFMs, etc) to close on validation coverage.
• Finding and implementing correct measure for failing tests.
• Continue to strive for innovation in problem-solving to improve test coverage in efforts to minimize project execution time while increasing efficiency.
• Understanding SoC/Subsystem validation environment, and providing IP validation support.

Qualifications

Required Qualifications

• Bachelor's degree in Electrical and Electronics Engineering, Computer Engineering, or a related field.
• 0-1 years of hands-on experience in RTL design verification with demonstrated skills gained through internships, academic projects, coursework, or hands-on training.
• Familiarity with System Verilog for design verification.
• Basic knowledge of Verilog or VHDL RTL design.
• Strong analytical and debugging skills, and creative in problem solving.
• Effective communication, collaboration, and initiative in diverse team environments.
• Positive energy and motivation to learn and adapt to evolving IP technologies and environments.

Preferred Qualifications

• Understanding of USB protocol fundamentals.
• Exposure to OVM/UVM verification methodology.
• Hands-on experience with AI coding assistants (GitHub Copilot, ChatGPT, or similar).
• Ability to critically evaluate AI-generated outputs for correctness.

Job Type: College Grad Shift: Shift 1 (Malaysia)

Primary Location: Malaysia, Penang

Additional Locations: Malaysia, Kulim

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Job posting details (such as work model, location or time type) are subject to change.

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices.