Senior Staff FPGA Interface Architect

Lattice Semiconductor; George Town; On-site; MYR 250,000 - 420,000; Full time

Job summary

Lattice Semiconductor is seeking a Senior Staff Engineer to lead development, integration, and productization of high‑performance interface solutions for next‑generation FPGA products. You will oversee RTL architecture, verification, and cross‑functional collaboration across hardware, software, and validation teams.

The role requires deep expertise in high‑speed interfaces, root‑cause analysis, and mentorship, with a focus on delivering reliable, silicon‑ready subsystems and silicon bring‑up

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 15+ years of ASIC/SoC/FPGA design and product development experience.
• Strong RTL design and subsystem integration skills.
• Experience with multiple high‑speed interfaces like PCIe, Ethernet, USB, MIPI, SerDes.

Responsibilities

• Lead architecture, RTL development, integration, verification, and productization of high‑speed interfaces.
• Own subsystem requirements across digital logic, PHY/PMA, soft IP, firmware, and tools.
• Drive root‑cause analysis for pre/post‑silicon and interoperability issues.
• Collaborate with software/firmware teams for configuration and diagnostics.
• Mentor engineers and improve design and release methodologies.

Skills

RTL design

ASIC/SoC/FPGA

high‑speed interfaces (PCIe/Ethernet/|

DFT/DFD

AI-assisted tooling

mentoring engineers

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

FPGA tools

Emulation platforms

FPGA prototyping

Job description

Lattice Semiconductor is seeking a Senior Staff Engineer to lead development, integration, and productization of high‑performance interface solutions for next‑generation FPGA products. You will oversee RTL architecture, verification, and cross‑functional collaboration across hardware, software, and validation teams.

The role requires deep expertise in high‑speed interfaces, root‑cause analysis, and mentorship, with a focus on delivering reliable, silicon‑ready subsystems and silicon bring‑up