PI/SI/STA Engineer

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; Presencial; MYR 60 000 - 90 000; Tempo integral

Resumo da oferta

XinPal Malaysia in Bayan Lepas, Penang seeks a PI/SI/STA Engineer to support signal and power integrity, timing analysis, and sign-off for advanced SoC and high‑performance packaging projects. You will run simulations, correlate results with lab or silicon data, and work with cross‑functional teams to mitigate risks.

Applicants should have a Bachelor’s or Master’s in EE or Physics and 2–3 years’ relevant industry experience, plus hands‑on use of Ansys, Sigrity and Synopsys PrimeTime/RedHawk.

Qualificações

• 2–3 years of experience in SI, PI or STA with exposure to modern packaging or high-speed designs.
• Solid understanding of high-speed interface behavior, parasitics and IR-drop effects on STA.
• Hands-on with electromagnetic, SI/PI, thermal or sign-off timing tools.

Responsabilidades

• Execute PI, SI and IR-drop-aware timing analysis to support design sign-off.
• Perform end-to-end simulations for PDN, high-speed channels, and thermal performance.
• Collaborate with package design, floorplanning, timing, and PHY/IO teams to resolve issues.

Conhecimentos

Signal Integrity

Power Integrity

STA

SI/PI analysis

Formação académica

Bachelor's in Electrical Engineering

Master's in Electrical Engineering or Physics

Ferramentas

Ansys

Sigrity

Synopsys PrimeTime/RedHawk

Descrição da oferta de emprego

XinPal Malaysia is part of an MNC headquartered in Singapore, specializing in delivering innovative technology solutions and supporting cutting-edge semiconductor projects. We are committed to building a high-performing team through innovation, collaboration, and continuous growth opportunities.

We are looking for a PI / SI / STA Engineer in Bayan Lepas, Penang to support signal integrity, power integrity, and timing analysis for advanced SoC, AI-SoC, and high-performance packaging designs. The role involves simulation, signoff analysis, silicon correlation, and cross-functional collaboration to identify and mitigate PI/SI/timing risks throughout the design cycle.

Execute PI, SI and IR-drop-aware timing analysis to support design signoff for high-performance packaging and complex SoC programs under senior guidance.

Perform end-to-end simulations for power delivery networks (PDN), high-speed signal channels, thermal performance, and power-integrity-induced timing degradation (IR-timing/EPS).

Support the correlation of simulation results against lab measurements or silicon data to refine modeling quality standards.

Collaborate with package design, floorplan, timing, and PHY/IO teams to resolve early-stage integration and layout issues.

Analyze and help mitigate risks related to dynamic/static IR drop, timing closure violations, jitter, crosstalk, insertion loss, and thermal hotspots.

Assist in EDA tool evaluation, model extraction, and automation flow development.

Bachelor's or Master's Degree in in Electrical Engineering, Physics or a related field.

Minimum 2-3 years of industry experience in Signal Integrity, Power integrity or STA , with exposure to modern packaging or high-speed designs.

Solid understanding of high-speed interface behavior, package parasitics, thermal analysis fundamentals, and IR-drop effects on static timing analysis (STA).

Hands-on experience with major electromagnetic, SI/PI, thermal, or signoff timing tools (e.g., Ansys, Sigrity, Synopsys PrimeTime / RedHawk).

Familiarity with packaging elements such as bumps, interposers, and RDL.