Senior SoC Timing & STA Engineer

SIGNOFF SEMICONDUCTORS PVT. LTD.; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

SIGNOFF SEMICONDUCTORS PVT. LTD. is seeking an experienced STA engineer to oversee sub-system and block-level STA convergence from early stages through signoff. You will participate in floorplanning and clock planning, and collaborate with design and DFT teams to define constraints and optimize runtime.

You will manage schedules and risk, prepare status reports for leads and customers, and work with large teams across multiple vendors to deliver high-quality SOC designs.

Qualifications

• 4–8 years of ASIC/SOC STA experience.
• Strong experience in ASIC timing constraints generation, validation and timing closure.
• Expertise in Tempus/Primetime and timing eco using Tempus ECO/PT-DMSA/Tweaker for sub-system and block-level.
• Experience in IO Timing budgeting and corner definitions.
• Familiarity with DFT.
• Proficient in scripting languages TCL and Python.
• Excellent timing and flow debugging skills.
• Experience in ECO generation flow for RTL, pre-physical and post-route considering timing, congestion and logic equivalence.
• Automation to improve PPA and ensure high-quality design environment for SOC.

Responsibilities

• Oversee sub-system/complex block-level STA convergence from early stages to signoff.
• Take part in sub-system/complex block-level floorplan and clock planning.
• Collaborate with logic design and DFT engineers to define constraints and optimize runtime.
• Manage schedules and risk tracking for STA deliverables.
• Prepare and present project status, risk and mitigation plans to leads and customer.
• Work effectively in large teams with multiple vendors.

Skills

ASIC timing

Timing closure

STA convergence

DFT familiarity

Scripting (TCL/Python)

Clock planning

Runtime optimization

Tools

Tempus

Primetime

Tweaker/PT-DMSA

Job description

SIGNOFF SEMICONDUCTORS PVT. LTD. is seeking an experienced STA engineer to oversee sub-system and block-level STA convergence from early stages through signoff. You will participate in floorplanning and clock planning, and collaborate with design and DFT teams to define constraints and optimize runtime.

You will manage schedules and risk, prepare status reports for leads and customers, and work with large teams across multiple vendors to deliver high-quality SOC designs.