Senior SoC DFT/DFX Architect

T-FOOTPRINT; Bayan Lepas; On-site; MYR 120,000 - 160,000; Full time

Job summary

T-FOOTPRINT is seeking a DFT/DFX Engineer with 3+ years of experience to support testability features for advanced SoC designs. You will work on DFT architecture, scan and memory test, ATPG, and DFT verification across design, physical design and validation teams.

Responsibilities include implementing DFT features, inserting scan, timing constraints, and test pattern development, while enabling production readiness and cross-team collaboration.

Qualifications

• 3+ years of hands-on DFT/DFX experience, including Scan, ATPG, MBIST, or Boundary Scan.
• Good understanding of digital SoC/ASIC design concepts (RTL/STA/verification).
• Experience with Verilog/SystemVerilog; VHDL knowledge is a plus.
• Proficiency in Tcl, Python, or Perl for flow automation and analysis.
• Strong analytical, debugging and cross-functional collaboration skills.

Responsibilities

• Participate in SoC-level DFT/DFX architecture and test strategy definition.
• Implement DFT features including Scan, Boundary Scan and MBIST.
• Perform scan insertion, test clock/reset implementation and test compression.
• Develop and optimize ATPG and production test patterns for coverage and efficiency.
• Generate and validate DFT timing constraints with design teams.
• Support DFT flow automation using Tcl and Python.
• Assist post-silicon bring-up and ATE debugging as needed.
• Evaluate DFT tools and methodologies to improve test quality.
• Collaborate with RTL, physical design, verification, and validation teams.

Skills

DFT/DFX methods

Scan

ATPG

MBIST

Boundary Scan

Test pattern

DFT timing

Scripting (Tcl/Python)

Debugging

Cross-functional teamwork

RTL/Verilog

STA/Design verification

Education

Bachelor's/Master's in ECE/CS

Tools

DFTMax

TestMAX

TetraMAX

Tessent

FastScan

Job description

T-FOOTPRINT is seeking a DFT/DFX Engineer with 3+ years of experience to support testability features for advanced SoC designs. You will work on DFT architecture, scan and memory test, ATPG, and DFT verification across design, physical design and validation teams.

Responsibilities include implementing DFT features, inserting scan, timing constraints, and test pattern development, while enabling production readiness and cross-team collaboration.